85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
2cfaa1aa1a
commit
e2b159d007
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@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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COBJS := $(BOARD).o law.o
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SOBJS := init.o
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#SOBJS :=
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -191,51 +191,3 @@ tlb1_entry:
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.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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entry_end
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x0fff_ffff DDR 256M
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
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* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* The defines below are 1-off of the actual LAWAR0 usage.
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* So LAWAR3 define uses the LAWAR4 register in the ECM.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long 4
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
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entry_end
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@ -0,0 +1,57 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x0fff_ffff DDR 256M
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
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* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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COBJS := $(BOARD).o law.o
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SOBJS := init.o
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#SOBJS :=
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -40,51 +40,6 @@
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mtlr r1 ; \
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blr ;
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(512M) -or- larger
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* c000_0000-cfff_ffff: PCI(256M)
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* d000_0000-dfff_ffff: RapidIO(256M)
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* e000_0000-ffff_ffff: localbus(512M)
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* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
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* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
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* e800_0000-efff_ffff: LBC 128M, nothing here
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* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
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* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
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* f800_0000-fdff_ffff: LBC 64M, nothing here
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* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
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* fd00_0000-fdff_ffff: LBC 16M, nothing here
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* fe00_0000-feff_ffff: LBC 16M, nothing here
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* ff00_0000-ff6f_ffff: LBC 7M, nothing here
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* ff70_0000-ff7f_ffff: CCSRBAR 1M
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* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long 0x03
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
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entry_end
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/* TLB1 entries configuration: */
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.section .bootpg, "ax"
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@ -0,0 +1,60 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(512M) -or- larger
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* c000_0000-cfff_ffff: PCI(256M)
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* d000_0000-dfff_ffff: RapidIO(256M)
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* e000_0000-ffff_ffff: localbus(512M)
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* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
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* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
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* e800_0000-efff_ffff: LBC 128M, nothing here
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* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
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* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
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* f800_0000-fdff_ffff: LBC 64M, nothing here
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* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
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* fd00_0000-fdff_ffff: LBC 16M, nothing here
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* fe00_0000-feff_ffff: LBC 16M, nothing here
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* ff00_0000-ff6f_ffff: LBC 7M, nothing here
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* ff70_0000-ff7f_ffff: CCSRBAR 1M
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* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
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SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -56,6 +56,7 @@
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#undef CONFIG_PCI /* pci ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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@ -56,6 +56,7 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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@ -50,6 +50,7 @@
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#undef CONFIG_PCI /* pci ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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