mxc_i2c: specify i2c base address in config file
The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
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@ -606,6 +606,13 @@ struct esdc_regs {
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#define UART4_BASE 0x43FB0000
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#define UART5_BASE 0x43FB4000
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#define I2C1_BASE_ADDR 0x43f80000
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#define I2C1_CLK_OFFSET 26
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#define I2C2_BASE_ADDR 0x43F98000
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#define I2C2_CLK_OFFSET 28
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#define I2C3_BASE_ADDR 0x43f84000
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#define I2C3_CLK_OFFSET 30
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#define ESDCTL_SDE (1 << 31)
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#define ESDCTL_CMD_RW (0 << 28)
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#define ESDCTL_CMD_PRECHARGE (1 << 28)
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@ -39,7 +39,7 @@
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#define MAX_BASE_ADDR 0x43F04000
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#define EVTMON_BASE_ADDR 0x43F08000
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#define CLKCTL_BASE_ADDR 0x43F0C000
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#define I2C_BASE_ADDR 0x43F80000
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#define I2C1_BASE_ADDR 0x43F80000
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#define I2C3_BASE_ADDR 0x43F84000
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#define ATA_BASE_ADDR 0x43F8C000
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#define UART1_BASE 0x43F90000
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@ -59,27 +59,10 @@ struct mxc_i2c_regs {
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#define I2SR_IIF (1 << 1)
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#define I2SR_RX_NO_AK (1 << 0)
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#if defined(CONFIG_SYS_I2C_MX31_PORT1)
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#define I2C_BASE 0x43f80000
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#define I2C_CLK_OFFSET 26
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#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
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#define I2C_BASE 0x43f98000
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#define I2C_CLK_OFFSET 28
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#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
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#define I2C_BASE 0x43f84000
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#define I2C_CLK_OFFSET 30
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#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
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#define I2C_BASE I2C1_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
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#define I2C_BASE I2C2_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
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#define I2C_BASE I2C_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
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#define I2C_BASE I2C2_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
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#define I2C_BASE I2C3_BASE_ADDR
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#ifdef CONFIG_SYS_I2C_BASE
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#define I2C_BASE CONFIG_SYS_I2C_BASE
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#else
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#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
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#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
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#endif
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#define I2C_MAX_TIMEOUT 10000
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@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
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(struct clock_control_regs *)CCM_BASE;
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/* start the required I2C clock */
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writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
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writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
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&sc_regs->cgr0);
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#endif
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@ -66,7 +66,7 @@
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX35_PORT3
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#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0xfe
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#define CONFIG_MXC_SPI
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@ -54,7 +54,8 @@
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX31_PORT2
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#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
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#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_MXC_UART
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@ -57,7 +57,7 @@
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX35_PORT1
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#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_MXC_SPI
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#define CONFIG_MXC_GPIO
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@ -50,7 +50,7 @@
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#define CONFIG_CMD_I2C
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX53_PORT2
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#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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/* MMC Configs */
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@ -53,7 +53,7 @@
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#define CONFIG_CMD_I2C
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX53_PORT2 1
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#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC Configs */
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@ -89,7 +89,7 @@
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/* I2C Configs */
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX53_PORT1
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#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC Controller */
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@ -50,7 +50,7 @@
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#define CONFIG_CMD_I2C
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MXC
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#define CONFIG_SYS_I2C_MX53_PORT2
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#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
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#define CONFIG_SYS_I2C_SPEED 100000
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/* MMC Configs */
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