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Merge branch 'master' of git://git.denx.de/u-boot-sh

This commit is contained in:
Wolfgang Denk 2008-09-01 00:03:40 +02:00
parent 845842c1e4 c75e772a2f
commit de5b094def
42 changed files with 4006 additions and 18 deletions

8
MAINTAINERS
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@ -753,12 +753,15 @@ Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
<iwamatsu.nobuhiro@renesas.com>
MS7750SE SH7750
MS7722SE SH7722
R7780MP SH7780
R2DPlus SH7751R
SH7763RDP SH7763
RSK7203 SH7203
AP325RXA SH7723
Mark Jonas <mark.jonas@de.bosch.com>
@ -767,6 +770,11 @@ Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
R0P77850011RL SH7785
Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
#########################################################################
# Blackfin Systems: #

8
MAKEALL
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@ -740,6 +740,9 @@ LIST_blackfin=" \
## SH Systems
#########################################################################
LIST_sh2=" \
rsk7203 \
"
LIST_sh3=" \
mpr2 \
ms7720se \
@ -752,9 +755,12 @@ LIST_sh4=" \
r7780mp \
r2dplus \
sh7763rdp \
sh7785lcr \
ap325rxa \
"
LIST_sh=" \
${LIST_sh2} \
${LIST_sh3} \
${LIST_sh4} \
"
@ -799,7 +805,7 @@ do
|mips|mips_el \
|nios|nios2 \
|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
|sh|sh3|sh4 \
|sh|sh2|sh3|sh4 \
|sparc \
|x86|I486 \
)

24
Makefile
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@ -3005,6 +3005,14 @@ mimc200_config : unconfig
# SH3 (SuperH)
#========================================================================
#########################################################################
## sh2 (Renesas SuperH)
#########################################################################
rsk7203_config: unconfig
@ >include/config.h
@echo "#define CONFIG_RSK7203 1" >> include/config.h
@./mkconfig -a $(@:_config=) sh sh2 rsk7203
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
@ -3041,17 +3049,27 @@ ms7722se_config : unconfig
r2dplus_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 r2dplus
@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus
r7780mp_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 r7780mp
@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp
sh7763rdp_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 sh7763rdp
@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp
sh7785lcr_config : unconfig
@ >include/config.h
@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr
ap325rxa_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa
#========================================================================
# SPARC

51
board/ap325rxa/Makefile Normal file
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@ -0,0 +1,51 @@
#########################################################################
#
# Copyright (C) 2008 Renesas Solutions Corp.
# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
#
# board/ap325rxa/Makefile
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := ap325rxa.o cpld-ap325rxa.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

162
board/ap325rxa/ap325rxa.c Normal file
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@ -0,0 +1,162 @@
/*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
/* PRI control register */
#define PRPRICR5 0xFF800048 /* LMB */
#define PRPRICR5_D 0x2a
/* FPGA control */
#define FPGA_NAND_CTL 0xB410020C
#define FPGA_NAND_RST 0x0008
#define FPGA_NAND_INIT 0x0000
#define FPGA_NAND_RST_WAIT 10000
/* I/O port data */
#define PACR_D 0x0000
#define PBCR_D 0x0000
#define PCCR_D 0x1000
#define PDCR_D 0x0000
#define PECR_D 0x0410
#define PFCR_D 0xffff
#define PGCR_D 0x0000
#define PHCR_D 0x5011
#define PJCR_D 0x4400
#define PKCR_D 0x7c00
#define PLCR_D 0x0000
#define PMCR_D 0x0000
#define PNCR_D 0x0000
#define PQCR_D 0x0000
#define PRCR_D 0x0000
#define PSCR_D 0x0000
#define PTCR_D 0x0010
#define PUCR_D 0x0fff
#define PVCR_D 0xffff
#define PWCR_D 0x0000
#define PXCR_D 0x7500
#define PYCR_D 0x0000
#define PZCR_D 0x5540
/* Pin Function Controler data */
#define PSELA_D 0x1410
#define PSELB_D 0x0140
#define PSELC_D 0x0000
#define PSELD_D 0x0400
/* I/O Buffer Hi-Z data */
#define HIZCRA_D 0x0000
#define HIZCRB_D 0x1000
#define HIZCRC_D 0x0000
#define HIZCRD_D 0x0000
/* Module select reg data */
#define MSELCRA_D 0x0014
#define MSELCRB_D 0x0018
/* Module Stop reg Data */
#define MSTPCR2_D 0xFFD9F280
/* CPLD loader */
extern void init_cpld(void);
int checkboard(void)
{
puts("BOARD: AP325RXA\n");
return 0;
}
int board_init(void)
{
/* Pin Function Controler Init */
outw(PSELA_D, PSELA);
outw(PSELB_D, PSELB);
outw(PSELC_D, PSELC);
outw(PSELD_D, PSELD);
/* I/O Buffer Hi-Z Init */
outw(HIZCRA_D, HIZCRA);
outw(HIZCRB_D, HIZCRB);
outw(HIZCRC_D, HIZCRC);
outw(HIZCRD_D, HIZCRD);
/* Module select reg Init */
outw(MSELCRA_D, MSELCRA);
outw(MSELCRB_D, MSELCRB);
/* Module Stop reg Init */
outl(MSTPCR2_D, MSTPCR2);
/* I/O ports */
outw(PACR_D, PACR);
outw(PBCR_D, PBCR);
outw(PCCR_D, PCCR);
outw(PDCR_D, PDCR);
outw(PECR_D, PECR);
outw(PFCR_D, PFCR);
outw(PGCR_D, PGCR);
outw(PHCR_D, PHCR);
outw(PJCR_D, PJCR);
outw(PKCR_D, PKCR);
outw(PLCR_D, PLCR);
outw(PMCR_D, PMCR);
outw(PNCR_D, PNCR);
outw(PQCR_D, PQCR);
outw(PRCR_D, PRCR);
outw(PSCR_D, PSCR);
outw(PTCR_D, PTCR);
outw(PUCR_D, PUCR);
outw(PVCR_D, PVCR);
outw(PWCR_D, PWCR);
outw(PXCR_D, PXCR);
outw(PYCR_D, PYCR);
outw(PZCR_D, PZCR);
/* PRI control register Init */
outl(PRPRICR5_D, PRPRICR5);
/* cpld init */
init_cpld();
return 0;
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
void led_set_state(unsigned short value)
{
}
void ide_set_reset(int idereset)
{
outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
udelay(FPGA_NAND_RST_WAIT);
outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
}

26
board/ap325rxa/config.mk Normal file
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@ -0,0 +1,26 @@
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x8FFC0000

206
board/ap325rxa/cpld-ap325rxa.c Normal file
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@ -0,0 +1,206 @@
/***************************************************************
* Project:
* CPLD SlaveSerial Configuration via embedded microprocessor.
*
* Copyright info:
*
* This is free software; you can redistribute it and/or modify
* it as you like.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Description:
*
* This is the main source file that will allow a microprocessor
* to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
* and Spartan-II devices via the SlaveSerial Configuration Mode.
* This code is discussed in Xilinx Application Note, XAPP502.
*
* History:
* 3-October-2001 MN/MP - Created
* 20-August-2008 Renesas Solutions - Modified to SH7723
****************************************************************/
#include <common.h>
/* Serial */
#define SCIF_BASE 0xffe00000 /* SCIF0 */
#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define RFCR (vu_long *)0xFE400020
#define SCSCR_INIT 0x0038
#define SCSCR_CLR 0x0000
#define SCFCR_INIT 0x0006
#define SCSMR_INIT 0x0080
#define RFCR_CLR 0xA400
#define SCI_TD_E 0x0020
#define SCI_TDRE_CLEAR 0x00df
#define BPS_SETTING_VALUE 1 /* 12.5MHz */
#define WAIT_RFCR_COUNTER 500
/* CPLD data size */
#define CPLD_DATA_SIZE 169216
/* out */
#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
#define CPLD_PROG_DAT 0x80
/* in */
#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
#define CPLD_INIT_DAT 0x40
#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
#define CPLD_DONE_DAT 0x20
#define HIZCRB ((vu_short *)0xA405015A)
/* data */
#define CPLD_NOMAL_START 0xA0A80000
#define CPLD_SAFE_START 0xA0AC0000
#define MODE_SW (vu_char *)0xA405012A
static void init_cpld_loader(void)
{
*SCSCR = SCSCR_CLR;
*SCFCR = SCFCR_INIT;
*SCSMR = SCSMR_INIT;
*SCBRR = BPS_SETTING_VALUE;
*RFCR = RFCR_CLR; /* Refresh counter clear */
while (*RFCR < WAIT_RFCR_COUNTER)
;
*SCFCR = 0x0; /* RTRG=00, TTRG=00 */
/* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
*SCSCR = SCSCR_INIT;
}
static int check_write_ready(void)
{
u16 status = *SC_SR;
return status & SCI_TD_E;
}
static void write_cpld_data(char ch)
{
while (!check_write_ready())
;
*SC_TDR = ch;
*SC_SR;
*SC_SR = SCI_TDRE_CLEAR;
}
static int delay(void)
{
int i;
int c = 0;
for (i = 0; i < 200; i++) {
c = *(volatile int *)0xa0000000;
}
return c;
}
/***********************************************************************
*
* Function: slave_serial
*
* Description: Initiates SlaveSerial Configuration.
* Calls ShiftDataOut() to output serial data
*
***********************************************************************/
static void slave_serial(void)
{
int i;
unsigned char *flash;
*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
delay();
/*
* Toggle Program Pin by Toggling Program_OE bit
* This is accomplished by writing to the Program Register in the CPLD
*
* NOTE: The Program_OE bit should be driven high to bring the Virtex
* Program Pin low. Likewise, it should be driven low
* to bring the Virtex Program Pin to High-Z
*/
*CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
delay();
/*
* Bring Program High-Z
* (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
*/
/* Program_OE bit Low brings the Virtex Program Pin to High Z: */
*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
delay();
/* Begin Slave-Serial Configuration */
flash = (unsigned char *)CPLD_NOMAL_START;
for (i = 0; i < CPLD_DATA_SIZE; i++)
write_cpld_data(*flash++);
}
/***********************************************************************
*
* Function: check_done_bit
*
* Description: This function takes monitors the CPLD Input Register
* by checking the status of the DONE bit in that Register.
* By doing so, it monitors the Xilinx Virtex device's DONE
* Pin to see if configuration bitstream has been properly
* loaded
*
***********************************************************************/
static void check_done_bit(void)
{
while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
;
}
/***********************************************************************
*
* Function: init_cpld
*
* Description: Begins Slave Serial configuration of Xilinx FPGA
*
***********************************************************************/
void init_cpld(void)
{
/* Init serial device */
init_cpld_loader();
if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
return;
*HIZCRB = 0x0000;
*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
/* write CPLD data from NOR flash to device */
slave_serial();
/*
* Monitor the DONE bit in the CPLD Input Register to see if
* configuration successful
*/
check_done_bit();
}

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board/ap325rxa/lowlevel_init.S Normal file
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@ -0,0 +1,243 @@
/*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
*
* board/ap325rxa/lowlevel_init.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
mov.l DRVCRA_A, r1
mov.l DRVCRA_D, r0
mov.w r0, @r1
mov.l DRVCRB_A, r1
mov.l DRVCRB_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D1, r0
mov.w r0, @r1
mov.l RWTCNT_A, r1
mov.l RWTCNT_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D2, r0
mov.w r0, @r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l r0, @r1
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
mov.l CS0BCR_A ,r1
mov.l CS0BCR_D ,r0
mov.l r0, @r1
mov.l CS4BCR_A ,r1
mov.l CS4BCR_D ,r0
mov.l r0, @r1
mov.l CS5ABCR_A ,r1
mov.l CS5ABCR_D ,r0
mov.l r0, @r1
mov.l CS5BBCR_A ,r1
mov.l CS5BBCR_D ,r0
mov.l r0, @r1
mov.l CS6ABCR_A ,r1
mov.l CS6ABCR_D ,r0
mov.l r0, @r1
mov.l CS6BBCR_A ,r1
mov.l CS6BBCR_D ,r0
mov.l r0, @r1
mov.l CS0WCR_A ,r1
mov.l CS0WCR_D ,r0
mov.l r0, @r1
mov.l CS4WCR_A ,r1
mov.l CS4WCR_D ,r0
mov.l r0, @r1
mov.l CS5AWCR_A ,r1
mov.l CS5AWCR_D ,r0
mov.l r0, @r1
mov.l CS5BWCR_A ,r1
mov.l CS5BWCR_D ,r0
mov.l r0, @r1
mov.l CS6AWCR_A ,r1
mov.l CS6AWCR_D ,r0
mov.l r0, @r1
mov.l CS6BWCR_A ,r1
mov.l CS6BWCR_D ,r0
mov.l r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D1, r0
mov.l r0, @r1
mov.l SBSC_SDWCR_A, r1
mov.l SBSC_SDWCR_D, r0
mov.l r0, @r1
mov.l SBSC_SDPCR_A, r1
mov.l SBSC_SDPCR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCSR_A, r1
mov.l SBSC_RTCSR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCNT_A, r1
mov.l SBSC_RTCNT_D, r0
mov.l r0, @r1
mov.l SBSC_RTCOR_A, r1
mov.l SBSC_RTCOR_D, r0
mov.l r0, @r1
mov.l SBSC_SDMR3_A1, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDMR3_A2, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SLEEP_CNT, r1
2: tst r1, r1
nop
bf/s 2b
dt r1
mov.l SBSC_SDMR3_A3, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D2, r0
mov.l r0, @r1
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l r0, @r1
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
rts
mov #0, r0
.align 2
DRVCRA_A: .long DRVCRA
DRVCRB_A: .long DRVCRB
DRVCRA_D: .long 0x4555
DRVCRB_D: .long 0x0005
RWTCSR_A: .long RWTCSR
RWTCNT_A: .long RWTCNT
FRQCR_A: .long FRQCR
RWTCSR_D1: .long 0xa507
RWTCSR_D2: .long 0xa504
RWTCNT_D: .long 0x5a00
FRQCR_D: .long 0x0b04474a
SBSC_SDCR_A: .long SBSC_SDCR
SBSC_SDWCR_A: .long SBSC_SDWCR
SBSC_SDPCR_A: .long SBSC_SDPCR
SBSC_RTCSR_A: .long SBSC_RTCSR
SBSC_RTCNT_A: .long SBSC_RTCNT
SBSC_RTCOR_A: .long SBSC_RTCOR
SBSC_SDMR3_A1: .long 0xfe510000
SBSC_SDMR3_A2: .long 0xfe500242
SBSC_SDMR3_A3: .long 0xfe5c0042
SBSC_SDCR_D1: .long 0x92810112
SBSC_SDCR_D2: .long 0x92810912
SBSC_SDWCR_D: .long 0x05162482
SBSC_SDPCR_D: .long 0x00300087
SBSC_RTCSR_D: .long 0xa55a0212
SBSC_RTCNT_D: .long 0xa55a0000
SBSC_RTCOR_D: .long 0xa55a0040
SBSC_SDMR3_D: .long 0x00
CMNCR_A: .long CMNCR
CS0BCR_A: .long CS0BCR
CS4BCR_A: .long CS4BCR
CS5ABCR_A: .long CS5ABCR
CS5BBCR_A: .long CS5BBCR
CS6ABCR_A: .long CS6ABCR
CS6BBCR_A: .long CS6BBCR
CS0WCR_A: .long CS0WCR
CS4WCR_A: .long CS4WCR
CS5AWCR_A: .long CS5AWCR
CS5BWCR_A: .long CS5BWCR
CS6AWCR_A: .long CS6AWCR
CS6BWCR_A: .long CS6BWCR
CMNCR_D: .long 0x00000013
CS0BCR_D: .long 0x24920400
CS4BCR_D: .long 0x24920400
CS5ABCR_D: .long 0x24920400
CS5BBCR_D: .long 0x7fff0600
CS6ABCR_D: .long 0x24920400
CS6BBCR_D: .long 0x24920600
CS0WCR_D: .long 0x00000480
CS4WCR_D: .long 0x00000480
CS5AWCR_D: .long 0x00000380
CS5BWCR_D: .long 0x00000600
CS6AWCR_D: .long 0x00000300
CS6BWCR_D: .long 0x00000540
CCR_A: .long 0xff00001c
CCR_D: .long 0x0000090d
SLEEP_CNT: .long 0x00000800
SR_MASK_D: .long 0xEFFFFF0F

106
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/*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
Base address of internal SDRAM is 0x88000000.
Although size of SDRAM can be either 16 or 32 MBytes,
we assume 16 MBytes (ie ignore upper half if the full
32 MBytes is present).
NOTE: This address must match with the definition of
TEXT_BASE in config.mk (in this directory).
*/
. = 0x88000000 + (128*1024*1024) - (256*1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/environment.o (.ppcenv)
. = ALIGN(8192);
common/environment.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

45
board/rsk7203/Makefile Normal file
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#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
# Copyright (C) 2008 Renesas Solutions Corp.
#
# u-boot/board/rsk7203/Makefile
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := rsk7203.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/rsk7203/config.mk Normal file
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#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
# Copyright (C) 2008 Renesas Solutions Corp.
#
# u-boot/board/rsk7203/config.mk
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x0C7C0000

265
board/rsk7203/lowlevel_init.S Normal file
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/*
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/processor.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
/* Cache setting */
mov.l CCR1_A ,r1
mov.l CCR1_D ,r0
mov.l r0,@r1
/* ConfigurePortPins */
mov.l PECRL3_A, r1
mov.l PECRL3_D, r0
mov.w r0,@r1
mov.l PCCRL4_A, r1
mov.l PCCRL4_D0, r0
mov.w r0,@r1
mov.l PECRL4_A, r1
mov.l PECRL4_D0, r0
mov.w r0,@r1
mov.l PEIORL_A, r1
mov.l PEIORL_D0, r0
mov.w r0,@r1
mov.l PCIORL_A, r1
mov.l PCIORL_D, r0
mov.w r0,@r1
mov.l PFCRH2_A, r1
mov.l PFCRH2_D, r0
mov.w r0,@r1
mov.l PFCRH3_A, r1
mov.l PFCRH3_D, r0
mov.w r0,@r1
mov.l PFCRH1_A, r1
mov.l PFCRH1_D, r0
mov.w r0,@r1
mov.l PFIORH_A, r1
mov.l PFIORH_D, r0
mov.w r0,@r1
mov.l PECRL1_A, r1
mov.l PECRL1_D0, r0
mov.w r0,@r1
mov.l PEIORL_A, r1
mov.l PEIORL_D1, r0
mov.w r0,@r1
/* Configure Operating Frequency */
mov.l WTCSR_A ,r1
mov.l WTCSR_D0 ,r0
mov.w r0,@r1
mov.l WTCSR_A ,r1
mov.l WTCSR_D1 ,r0
mov.w r0,@r1
mov.l WTCNT_A ,r1
mov.l WTCNT_D ,r0
mov.w r0,@r1
/* Set clock mode*/
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
/* Configure Bus And Memory */
init_bsc_cs0:
mov.l PCCRL4_A,r1
mov.l PCCRL4_D1,r0
mov.w r0,@r1
mov.l PECRL1_A,r1
mov.l PECRL1_D1,r0
mov.w r0,@r1
mov.l CMNCR_A,r1
mov.l CMNCR_D,r0
mov.l r0,@r1
mov.l SC0BCR_A,r1
mov.l SC0BCR_D,r0
mov.l r0,@r1
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
init_bsc_cs1:
mov.l PECRL4_A,r1
mov.l PECRL4_D1,r0
mov.w r0,@r1
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
init_sdram:
mov.l PCCRL2_A,r1
mov.l PCCRL2_D,r0
mov.w r0,@r1
mov.l PCCRL4_A,r1
mov.l PCCRL4_D2,r0
mov.w r0,@r1
mov.l PCCRL1_A,r1
mov.l PCCRL1_D,r0
mov.w r0,@r1
mov.l PCCRL3_A,r1
mov.l PCCRL3_D,r0
mov.w r0,@r1
mov.l CS3BCR_A,r1
mov.l CS3BCR_D,r0
mov.l r0,@r1
mov.l CS3WCR_A,r1
mov.l CS3WCR_D,r0
mov.l r0,@r1
mov.l SDCR_A,r1
mov.l SDCR_D,r0
mov.l r0,@r1
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.l r0,@r1
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.l r0,@r1
/* wait 200us */
mov.l REPEAT_D,r3
mov #0,r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
nop
mov.l SDRAM_MODE, r1
mov #0,r0
mov.l r0, @r1
nop
rts
.align 4
CCR1_A: .long CCR1
CCR1_D: .long 0x0000090B
PCCRL4_A: .long 0xFFFE3910
PCCRL4_D0: .long 0x00000000
PECRL4_A: .long 0xFFFE3A10
PECRL4_D0: .long 0x00000000
PECRL3_A: .long 0xFFFE3A12
PECRL3_D: .long 0x00000000
PEIORL_A: .long 0xFFFE3A06
PEIORL_D0: .long 0x00001C00
PEIORL_D1: .long 0x00001C02
PCIORL_A: .long 0xFFFE3906
PCIORL_D: .long 0x00004000
PFCRH2_A: .long 0xFFFE3A8C
PFCRH2_D: .long 0x00000000
PFCRH3_A: .long 0xFFFE3A8A
PFCRH3_D: .long 0x00000000
PFCRH1_A: .long 0xFFFE3A8E
PFCRH1_D: .long 0x00000000
PFIORH_A: .long 0xFFFE3A84
PFIORH_D: .long 0x00000729
PECRL1_A: .long 0xFFFE3A16
PECRL1_D0: .long 0x00000033
WTCSR_A: .long 0xFFFE0000
WTCSR_D0: .long 0x0000A518
WTCSR_D1: .long 0x0000A51D
WTCNT_A: .long 0xFFFE0002
WTCNT_D: .long 0x00005A84
FRQCR_A: .long 0xFFFE0010
FRQCR_D: .long 0x00000104
PCCRL4_D1: .long 0x00000010
PECRL1_D1: .long 0x00000133
CMNCR_A: .long 0xFFFC0000
CMNCR_D: .long 0x00001810
SC0BCR_A: .long 0xFFFC0004
SC0BCR_D: .long 0x10000400
CS0WCR_A: .long 0xFFFC0028
CS0WCR_D: .long 0x00000B41
PECRL4_D1: .long 0x00000100
CS1WCR_A: .long 0xFFFC002C
CS1WCR_D: .long 0x00000B01
PCCRL4_D2: .long 0x00000011
PCCRL3_A: .long 0xFFFE3912
PCCRL3_D: .long 0x00000011
PCCRL2_A: .long 0xFFFE3914
PCCRL2_D: .long 0x00001111
PCCRL1_A: .long 0xFFFE3916
PCCRL1_D: .long 0x00001010
PDCRL4_A: .long 0xFFFE3990
PDCRL4_D: .long 0x00000011
PDCRL3_A: .long 0xFFFE3992
PDCRL3_D: .long 0x00000011
PDCRL2_A: .long 0xFFFE3994
PDCRL2_D: .long 0x00001111
PDCRL1_A: .long 0xFFFE3996
PDCRL1_D: .long 0x00001000
CS3BCR_A: .long 0xFFFC0010
CS3BCR_D: .long 0x00004400
CS3WCR_A: .long 0xFFFC0034
CS3WCR_D: .long 0x00002892
SDCR_A: .long 0xFFFC004C
SDCR_D: .long 0x00000809
RTCOR_A: .long 0xFFFC0058
RTCOR_D: .long 0xA55A0041
RTCSR_A: .long 0xFFFC0050
RTCSR_D: .long 0xa55a0010
STBCR3_A: .long 0xFFFE0408
STBCR3_D: .long 0x00000000
STBCR4_A: .long 0xFFFE040C
STBCR4_D: .long 0x00000008
STBCR5_A: .long 0xFFFE0410
STBCR5_D: .long 0x00000000
STBCR6_A: .long 0xFFFE0414
STBCR6_D: .long 0x00000002
SDRAM_MODE: .long 0xFFFC5040
REPEAT_D: .long 0x00009C40

50
board/rsk7203/rsk7203.c Normal file
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/*
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
*
* u-boot/board/rsk7203/rsk7203.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7203\n");
return 0;
}
int board_init(void)
{
return 0;
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
void led_set_state(unsigned short value)
{
}

101
board/rsk7203/u-boot.lds Normal file
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/*
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
* Base address of internal SDRAM is 0x0C000000.
*
* NOTE: This address must match with the definition of
*TEXT_BASE in config.mk (in this directory).
*/
. = 0x0C000000 + (8*1024*1024) - (256*1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh2/start.o (.text)
. = ALIGN(8192);
common/environment.o (.ppcenv)
. = ALIGN(8192);
common/environment.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

42
board/sh7785lcr/Makefile Normal file
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#
# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

26
board/sh7785lcr/config.mk Normal file
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#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x0ff80000

318
board/sh7785lcr/lowlevel_init.S Normal file
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/processor.h>
.macro write32, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.l r0, @r1
.endm
.macro write16, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.w r0, @r1
.endm
.macro write8, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.b r0, @r1
.endm
.macro wait_timer, time
mov.l \time ,r3
1:
nop
tst r3, r3
bf/s 1b
dt r3
.endm
#include <asm/processor.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
wait_timer WAIT_200US
wait_timer WAIT_200US
/*------- LBSC -------*/
write32 MMSELR_A, MMSELR_D
/*------- DBSC2 -------*/
write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
wait_timer WAIT_200US
write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
wait_timer WAIT_200US
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
wait_timer WAIT_200US
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
write32 DBSC2_DBEN_A, DBSC2_DBEN_D
write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
wait_timer WAIT_200US
/*------- GPIO -------*/
write16 PACR_A, PACR_D
write16 PBCR_A, PBCR_D
write16 PCCR_A, PCCR_D
write16 PDCR_A, PDCR_D
write16 PECR_A, PECR_D
write16 PFCR_A, PFCR_D
write16 PGCR_A, PGCR_D
write16 PHCR_A, PHCR_D
write16 PJCR_A, PJCR_D
write16 PKCR_A, PKCR_D
write16 PLCR_A, PLCR_D
write16 PMCR_A, PMCR_D
write16 PNCR_A, PNCR_D
write16 PPCR_A, PPCR_D
write16 PQCR_A, PQCR_D
write16 PRCR_A, PRCR_D
write8 PEPUPR_A, PEPUPR_D
write8 PHPUPR_A, PHPUPR_D
write8 PJPUPR_A, PJPUPR_D
write8 PKPUPR_A, PKPUPR_D
write8 PLPUPR_A, PLPUPR_D
write8 PMPUPR_A, PMPUPR_D
write8 PNPUPR_A, PNPUPR_D
write16 PPUPR1_A, PPUPR1_D
write16 PPUPR2_A, PPUPR2_D
write16 P1MSELR_A, P1MSELR_D
write16 P2MSELR_A, P2MSELR_D
/*------- LBSC -------*/
write32 BCR_A, BCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS1BCR_A, CS1BCR_D
write32 CS1WCR_A, CS1WCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS4WCR_A, CS4WCR_D
mov.l PASCR_A, r0
mov.l @r0, r2
mov.l PASCR_32BIT_MODE, r1
tst r1, r2
bt lbsc_29bit
write32 CS2BCR_A, CS_USB_BCR_D
write32 CS2WCR_A, CS_USB_WCR_D
write32 CS3BCR_A, CS_SD_BCR_D
write32 CS3WCR_A, CS_SD_WCR_D
write32 CS5BCR_A, CS_I2C_BCR_D
write32 CS5WCR_A, CS_I2C_WCR_D
write32 CS6BCR_A, CS0BCR_D
write32 CS6WCR_A, CS0WCR_D
bra lbsc_end
nop
lbsc_29bit:
write32 CS5BCR_A, CS_USB_BCR_D
write32 CS5WCR_A, CS_USB_WCR_D
write32 CS6BCR_A, CS_SD_BCR_D
write32 CS6WCR_A, CS_SD_WCR_D
lbsc_end:
write32 CCR_A, CCR_D
rts
nop
.align 4
/*------- LBSC -------*/
MMSELR_A: .long 0xfc400020
MMSELR_D: .long 0xa5a50002
/*------- DBSC2 -------*/
#define DBSC2_BASE 0xfe800000
DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54
DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
DDR_DUMMY_ACCESS_A: .long 0x40000000
DBSC2_DBCONF_D: .long 0x00630002
DBSC2_DBTR0_D: .long 0x050b1f04
DBSC2_DBTR1_D: .long 0x00040204
DBSC2_DBTR2_D: .long 0x02100308
DBSC2_DBFREQ_D1: .long 0x00000000
DBSC2_DBFREQ_D2: .long 0x00000100
DBSC2_DBDICODTOCD_D: .long 0x000f0907
DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
DBSC2_DBCMDCNT_D_REF: .long 0x00000004
DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
DBSC2_DBEN_D: .long 0x00000001
DBSC2_DBPDCNT0_D3: .long 0x00000080
DBSC2_DBRFCNT1_D: .long 0x00000926
DBSC2_DBRFCNT2_D: .long 0x00fe00fe
DBSC2_DBRFCNT0_D: .long 0x00010000
WAIT_200US: .long 33333
/*------- GPIO -------*/
#define GPIO_BASE 0xffe70000
PACR_A: .long GPIO_BASE + 0x00
PBCR_A: .long GPIO_BASE + 0x02
PCCR_A: .long GPIO_BASE + 0x04
PDCR_A: .long GPIO_BASE + 0x06
PECR_A: .long GPIO_BASE + 0x08
PFCR_A: .long GPIO_BASE + 0x0a
PGCR_A: .long GPIO_BASE + 0x0c
PHCR_A: .long GPIO_BASE + 0x0e
PJCR_A: .long GPIO_BASE + 0x10
PKCR_A: .long GPIO_BASE + 0x12
PLCR_A: .long GPIO_BASE + 0x14
PMCR_A: .long GPIO_BASE + 0x16
PNCR_A: .long GPIO_BASE + 0x18
PPCR_A: .long GPIO_BASE + 0x1a
PQCR_A: .long GPIO_BASE + 0x1c
PRCR_A: .long GPIO_BASE + 0x1e
PEPUPR_A: .long GPIO_BASE + 0x48
PHPUPR_A: .long GPIO_BASE + 0x4e
PJPUPR_A: .long GPIO_BASE + 0x50
PKPUPR_A: .long GPIO_BASE + 0x52
PLPUPR_A: .long GPIO_BASE + 0x54
PMPUPR_A: .long GPIO_BASE + 0x56
PNPUPR_A: .long GPIO_BASE + 0x58
PPUPR1_A: .long GPIO_BASE + 0x60
PPUPR2_A: .long GPIO_BASE + 0x62
P1MSELR_A: .long GPIO_BASE + 0x80
P2MSELR_A: .long GPIO_BASE + 0x82
PACR_D: .long 0x0000
PBCR_D: .long 0x0000
PCCR_D: .long 0x0000
PDCR_D: .long 0x0000
PECR_D: .long 0x0000
PFCR_D: .long 0x0000
PGCR_D: .long 0x0000
PHCR_D: .long 0x00c0
PJCR_D: .long 0xc3fc
PKCR_D: .long 0x03ff
PLCR_D: .long 0x0000
PMCR_D: .long 0xffff
PNCR_D: .long 0xf0c3
PPCR_D: .long 0x0000
PQCR_D: .long 0x0000
PRCR_D: .long 0x0000
PEPUPR_D: .long 0xff
PHPUPR_D: .long 0x00
PJPUPR_D: .long 0x00
PKPUPR_D: .long 0x00
PLPUPR_D: .long 0x00
PMPUPR_D: .long 0xfc
PNPUPR_D: .long 0x00
PPUPR1_D: .long 0xffbf
PPUPR2_D: .long 0xff00
P1MSELR_D: .long 0x3780
P2MSELR_D: .long 0x0000
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS0WCR_A: .long CS0WCR
CS1BCR_A: .long CS1BCR
CS1WCR_A: .long CS1WCR
CS2BCR_A: .long CS2BCR
CS2WCR_A: .long CS2WCR
CS3BCR_A: .long CS3BCR
CS3WCR_A: .long CS3WCR
CS4BCR_A: .long CS4BCR
CS4WCR_A: .long CS4WCR
CS5BCR_A: .long CS5BCR
CS5WCR_A: .long CS5WCR
CS6BCR_A: .long CS6BCR
CS6WCR_A: .long CS6WCR
BCR_D: .long 0x80000003
CS0BCR_D: .long 0x22222340
CS0WCR_D: .long 0x00111118
CS1BCR_D: .long 0x11111100
CS1WCR_D: .long 0x33333303
CS4BCR_D: .long 0x11111300
CS4WCR_D: .long 0x00101012
/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
CS_USB_BCR_D: .long 0x11111200
CS_USB_WCR_D: .long 0x00020004
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
CS_SD_BCR_D: .long 0x00000300
CS_SD_WCR_D: .long 0x00030108
/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
CS_I2C_BCR_D: .long 0x11111100
CS_I2C_WCR_D: .long 0x00000003
CCR_A: .long 0xff00001c
CCR_D: .long 0x0000090b

58
board/sh7785lcr/rtl8169.h Normal file
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr))
#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr))
#define PCI_PAR PCIREG_32(0xfe0401c0)
#define PCI_PDR PCIREG_32(0xfe040220)
#define PCI_CR PCIREG_32(0xfe040100)
#define PCI_CONF1 PCIREG_32(0xfe040004)
#define HIGH 1
#define LOW 0
#define PCI_PROG 0x80
#define PCI_EEP_ADDRESS (unsigned short)0x0007
#define PCI_MAC_ADDRESS_SIZE 3
#define TIME1 100
#define TIME2 20000
#define BIT_DUMMY 0
#define MAC_EEP_READ 1
#define MAC_EEP_WRITE 2
#define MAC_EEP_ERACE 3
#define MAC_EEP_EWEN 4
#define MAC_EEP_EWDS 5
/* RTL8169 */
const unsigned short EEPROM_W_Data_8169_A[] = {
0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
0x4020, 0xa101
};
const unsigned short EEPROM_W_Data_8169_B[] = {
0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};

349
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "rtl8169.h"
static unsigned char *PCI_MEMR;
static void mac_delay(unsigned int cnt)
{
udelay(cnt);
}
static void mac_pci_setup(void)
{
unsigned long pci_data;
PCI_PAR = 0x00000010;
PCI_PDR = 0x00001000;
PCI_PAR = 0x00000004;
pci_data = PCI_PDR;
PCI_PDR = pci_data | 0x00000007;
PCI_PAR = 0x00000010;
PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
}
static void EECS(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x08;
else
*PCI_MEMR = data & 0xf7;
}
static void EECLK(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x04;
else
*PCI_MEMR = data & 0xfb;
}
static void EEDI(int level)
{
unsigned char data = *PCI_MEMR;
if (level)
*PCI_MEMR = data | 0x02;
else
*PCI_MEMR = data & 0xfd;
}
static inline void sh7785lcr_bitset(unsigned short bit)
{
if (bit)
EEDI(HIGH);
else
EEDI(LOW);
EECLK(LOW);
mac_delay(TIME1);
EECLK(HIGH);
mac_delay(TIME1);
EEDI(LOW);
}
static inline unsigned char sh7785lcr_bitget(void)
{
unsigned char bit;
EECLK(LOW);
mac_delay(TIME1);
bit = *PCI_MEMR & 0x01;
EECLK(HIGH);
mac_delay(TIME1);
return bit;
}
static inline void sh7785lcr_setcmd(unsigned char command)
{
sh7785lcr_bitset(BIT_DUMMY);
switch (command) {
case MAC_EEP_READ:
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
break;
case MAC_EEP_WRITE:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(1);
break;
case MAC_EEP_ERACE:
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
break;
case MAC_EEP_EWEN:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(0);
break;
case MAC_EEP_EWDS:
sh7785lcr_bitset(1);
sh7785lcr_bitset(0);
sh7785lcr_bitset(0);
break;
default:
break;
}
}
static inline unsigned short sh7785lcr_getdt(void)
{
unsigned short data = 0;
int i;
sh7785lcr_bitget(); /* DUMMY */
for (i = 0 ; i < 16 ; i++) {
data <<= 1;
data |= sh7785lcr_bitget();
}
return data;
}
static inline void sh7785lcr_setadd(unsigned short address)
{
sh7785lcr_bitset(address & 0x0020); /* A5 */
sh7785lcr_bitset(address & 0x0010); /* A4 */
sh7785lcr_bitset(address & 0x0008); /* A3 */
sh7785lcr_bitset(address & 0x0004); /* A2 */
sh7785lcr_bitset(address & 0x0002); /* A1 */
sh7785lcr_bitset(address & 0x0001); /* A0 */
}
static inline void sh7785lcr_setdata(unsigned short data)
{
sh7785lcr_bitset(data & 0x8000);
sh7785lcr_bitset(data & 0x4000);
sh7785lcr_bitset(data & 0x2000);
sh7785lcr_bitset(data & 0x1000);
sh7785lcr_bitset(data & 0x0800);
sh7785lcr_bitset(data & 0x0400);
sh7785lcr_bitset(data & 0x0200);
sh7785lcr_bitset(data & 0x0100);
sh7785lcr_bitset(data & 0x0080);
sh7785lcr_bitset(data & 0x0040);
sh7785lcr_bitset(data & 0x0020);
sh7785lcr_bitset(data & 0x0010);
sh7785lcr_bitset(data & 0x0008);
sh7785lcr_bitset(data & 0x0004);
sh7785lcr_bitset(data & 0x0002);
sh7785lcr_bitset(data & 0x0001);
}
static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
unsigned int count)
{
unsigned int i;
for (i = 0; i < count; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_WRITE);
sh7785lcr_setadd(address++);
sh7785lcr_setdata(*(data + i));
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
mac_delay(TIME2);
}
}
static void sh7785lcr_macerase(void)
{
unsigned int i;
unsigned short pci_address = 7;
for (i = 0; i < 3; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_ERACE);
sh7785lcr_setadd(pci_address++);
mac_delay(TIME1);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
}
mac_delay(TIME2);
printf("\n\nErace End\n");
for (i = 0; i < 10; i++)
mac_delay(TIME2);
}
static void sh7785lcr_macwrite(unsigned short *data)
{
sh7785lcr_macerase();
sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
}
void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
{
unsigned int i;
unsigned short wk;
for (i = 0 ; i < count; i++) {
EECS(HIGH);
EEDI(LOW);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_READ);
sh7785lcr_setadd(address++);
wk = sh7785lcr_getdt();
*buf++ = (unsigned char)(wk & 0xff);
*buf++ = (unsigned char)((wk >> 8) & 0xff);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
}
}
static void sh7785lcr_macadrd(unsigned char *buf)
{
*PCI_MEMR = PCI_PROG;
sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
}
static void sh7785lcr_eepewen(void)
{
*PCI_MEMR = PCI_PROG;
mac_delay(TIME1);
EECS(LOW);
EECLK(LOW);
EEDI(LOW);
EECS(HIGH);
mac_delay(TIME1);
sh7785lcr_setcmd(MAC_EEP_EWEN);
sh7785lcr_bitset(1);
sh7785lcr_bitset(1);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
sh7785lcr_bitset(BIT_DUMMY);
EECLK(LOW);
EEDI(LOW);
EECS(LOW);
mac_delay(TIME1);
}
void mac_write(unsigned short *data)
{
mac_pci_setup();
sh7785lcr_eepewen();
sh7785lcr_macwrite(data);
}
void mac_read(void)
{
unsigned char data[6];
mac_pci_setup();
sh7785lcr_macadrd(data);
printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
data[0], data[1], data[2], data[3], data[4], data[5]);
}
int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
unsigned char mac[6];
char *s, *e;
if (argc != 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
s = argv[1];
for (i = 0; i < 6; i++) {
mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
mac_write((unsigned short *)mac);
return 0;
}
U_BOOT_CMD(
setmac, 2, 1, do_set_mac,
"setmac - write MAC address for RTL8110SCL\n",
"\n"
"setmac <mac address> - write MAC address for RTL8110SCL\n"
);
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc != 1) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
mac_read();
return 0;
}
U_BOOT_CMD(
printmac, 1, 1, do_print_mac,
"printmac - print MAC address for RTL8110\n",
"\n"
" - print MAC address for RTL8110\n"
);

173
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/pci.h>
#if defined(CONFIG_CPU_32BIT)
#define NOCACHE_OFFSET 0x00000000
#else
#define NOCACHE_OFFSET 0xa0000000
#endif
#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET)
#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET)
#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET)
#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET)
static void wait_ms(unsigned long time)
{
while (time--)
udelay(1000);
}
static void test_pld(void)
{
printf("PLD version = %04x\n", readb(PLD_VERSR));
}
static void test_sm107(void)
{
printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
}
static void test_led(void)
{
printf("turn on LEDs 3, 5, 7, 9\n");
writeb(0x55, PLD_LEDCR);
wait_ms(2000);
printf("turn on LEDs 4, 6, 8, 10\n");
writeb(0xaa, PLD_LEDCR);
wait_ms(2000);
writeb(0x00, PLD_LEDCR);
}
static void test_dipsw(void)
{
printf("Please DIPSW set = B'0101\n");
while (readb(PLD_SWSR) != 0x05) {
if (ctrlc())
return;
}
printf("Please DIPSW set = B'1010\n");
while (readb(PLD_SWSR) != 0x0A) {
if (ctrlc())
return;
}
printf("DIPSW OK\n");
}
static void test_net(void)
{
unsigned long data;
writel(0x80000000, 0xfe0401c0);
data = readl(0xfe040220);
if (data == 0x816910ec)
printf("Ethernet OK\n");
else
printf("Ethernet NG, data = %08x\n", data);
}
static void test_sata(void)
{
unsigned long data;
writel(0x80000800, 0xfe0401c0);
data = readl(0xfe040220);
if (data == 0x35121095)
printf("SATA OK\n");
else
printf("SATA NG, data = %08x\n", data);
}
static void test_pci(void)
{
writel(0x80001800, 0xfe0401c0);
printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
writel(0x80001000, 0xfe0401c0);
printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
}
int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *cmd;
if (argc != 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
cmd = argv[1];
switch (cmd[0]) {
case 'a': /* all */
test_pld();
test_led();
test_dipsw();
test_sm107();
test_net();
test_sata();
test_pci();
break;
case 'p': /* pld or pci */
if (cmd[1] == 'l')
test_pld();
else
test_pci();
break;
case 'l': /* led */
test_led();
break;
case 'd': /* dipsw */
test_dipsw();
break;
case 's': /* sm107 or sata */
if (cmd[1] == 'm')
test_sm107();
else
test_sata();
break;
case 'n': /* net */
test_net();
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(
hwtest, 2, 1, do_hw_test,
"hwtest - hardware test for R0P7785LC0011RL board\n",
"\n"
"hwtest all - test all hardware\n"
"hwtest pld - output PLD version\n"
"hwtest led - turn on LEDs\n"
"hwtest dipsw - test DIP switch\n"
"hwtest sm107 - output SM107 version\n"
"hwtest net - check RTL8110 ID\n"
"hwtest sata - check SiI3512 ID\n"
"hwtest pci - output PCI slot device ID\n"
);

51
board/sh7785lcr/sh7785lcr.c Normal file
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/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/pci.h>
int checkboard(void)
{
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
return 0;
}
int board_init(void)
{
return 0;
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
static struct pci_controller hose;
void pci_init_board(void)
{
pci_sh7780_init(&hose);
}

97
board/sh7785lcr/u-boot.lds Normal file
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/*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/environment.o (.ppcenv)
. = ALIGN(8192);
common/environment.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

49
cpu/sh2/Makefile Normal file
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@ -0,0 +1,49 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Copyright (C) 2008 Renesas Solutions Corp.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
OBJS = cpu.o interrupts.o watchdog.o time.o # cache.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

112
cpu/sh2/cache.c Normal file
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@ -0,0 +1,112 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#define CACHE_VALID 1
#define CACHE_UPDATED 2
static inline void cache_wback_all(void)
{
unsigned long addr, data, i, j;
jump_to_P2();
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
addr = CACHE_OC_ADDRESS_ARRAY
| (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
data &= ~CACHE_UPDATED;
outl(data, addr);
}
}
}
back_to_P1();
}
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
int cache_control(unsigned int cmd)
{
unsigned long ccr;
jump_to_P2();
ccr = inl(CCR);
if (ccr & CCR_CACHE_ENABLE)
cache_wback_all();
if (cmd == CACHE_DISABLE)
outl(CCR_CACHE_STOP, CCR);
else
outl(CCR_CACHE_INIT, CCR);
back_to_P1();
return 0;
}

26
cpu/sh2/config.mk Normal file
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@ -0,0 +1,26 @@
#
# (C) Copyright 2007-2008
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
PLATFORM_CPPFLAGS += -m3e -mb
PLATFORM_RELFLAGS += -ffixed-r13
PLATFORM_LDFLAGS += -EB

98
cpu/sh2/cpu.c Normal file
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@ -0,0 +1,98 @@
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#define STBCR4 0xFFFE040C
#define cmt_clock_enable() do {\
writeb(readb(STBCR4) & ~0x04, STBCR4);\
} while (0)
#define scif0_enable() do {\
writeb(readb(STBCR4) & ~0x80, STBCR4);\
} while (0)
int checkcpu(void)
{
#if defined(CONFIG_SH2A)
puts("CPU: SH2A\n");
#else
puts("CPU: SH2\n");
#endif
return 0;
}
int cpu_init(void)
{
/* SCIF enable */
scif0_enable();
/* CMT clock enable */
cmt_clock_enable() ;
return 0;
}
int cleanup_before_linux(void)
{
disable_interrupts();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
disable_interrupts();
reset_cpu(0);
return 0;
}
void flush_cache(unsigned long addr, unsigned long size)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}

39
cpu/sh2/interrupts.c Normal file
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@ -0,0 +1,39 @@
/*
* Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

78
cpu/sh2/start.S Normal file
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@ -0,0 +1,78 @@
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
.text
.align 2
.global _start
_start:
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
.long 0x00000000
_init:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
mov.l ._sh_generic_init, r0
jsr @r0
nop
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long reloc_dst
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init

111
cpu/sh2/time.c Normal file
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@ -0,0 +1,111 @@
/*
* Copyright (C) 2007,2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
#define CMT_CMCSR_CALIB 0x0000
#define CMT_MAX_COUNTER (0xFFFFFFFF)
#define CMT_TIMER_RESET (0xFFFF)
static vu_long cmt0_timer;
static void cmt_timer_start(unsigned int timer)
{
writew(readw(CMSTR) | 0x01, CMSTR);
}
static void cmt_timer_stop(unsigned int timer)
{
writew(readw(CMSTR) & ~0x01, CMSTR);
}
int timer_init(void)
{
cmt0_timer = 0;
/* Divide clock by 32 */
readw(CMCSR_0);
writew(CMT_CMCSR_INIT, CMCSR_0);
/* User Device 0 only */
cmt_timer_stop(0);
set_timer(CMT_TIMER_RESET);
cmt_timer_start(0);
return 0;
}
unsigned long long get_ticks(void)
{
return cmt0_timer;
}
static vu_long cmcnt;
ulong get_timer(ulong base)
{
ulong data = readw(CMCNT_0);
if (data >= cmcnt)
cmcnt = data - cmcnt;
else
cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
else
cmt0_timer += cmcnt;
cmcnt = data;
return cmt0_timer - base;
}
void set_timer(ulong t)
{
writew((u16) t, CMCOR_0);
}
void reset_timer(void)
{
cmt_timer_stop(0);
set_timer(CMT_TIMER_RESET);
cmt0_timer = 0;
cmt_timer_start(0);
}
void udelay(unsigned long usec)
{
unsigned int start = get_timer(0);
while (get_timer((ulong) start) < (usec * (CFG_HZ / 1000000)))
continue;
}
unsigned long get_tbclk(void)
{
return CFG_HZ;
}

33
cpu/sh2/watchdog.c Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhoro@renesas.com>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
int watchdog_init(void)
{
return 0;
}
void reset_cpu(unsigned long ignored)
{
while (1)
;
}

83
doc/README.sh7785lcr Normal file
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@ -0,0 +1,83 @@
========================================
Renesas Technology R0P7785LC0011RL board
========================================
This board specification:
=========================
The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
- SH7785 (SH-4A)
- DDR2-SDRAM 512MB
- NOR Flash 64MB
- 2D Graphic controller
- SATA controller
- Ethernet controller
- USB host/peripheral controller
- SD controller
- I2C controller
- RTC
This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
phys address | S2-5 = OFF | S2-5 = ON
-------------------------------+---------------+---------------
0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
0x04000000 - 0x05ffffff(CS1) | PLD | PLD
0x06000000 - 0x07ffffff(CS1) | reserved | I2C
0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
0x14000000 - 0x17ffffff(CS5) | I2C | USB
0x18000000 - 0x1bffffff(CS6) | reserved | SD
0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
This board specific command:
============================
This board has the following its specific command:
- hwtest
- printmac
- setmac
1. hwtest
This is self-check command. This command has the following options:
- all : test all hardware
- pld : output PLD version
- led : turn on LEDs
- dipsw : test DIP switch
- sm107 : output SM107 version
- net : check RTL8110 ID
- sata : check SiI3512 ID
- net : output PCI slot device ID
i.e)
=> hwtest led
turn on LEDs 3, 5, 7, 9
turn on LEDs 4, 6, 8, 10
=> hwtest net
Ethernet OK
2. printmac
This command outputs MAC address of this board.
i.e)
=> printmac
MAC = 00:00:87:**:**:**
3. setmac
This command writes MAC address of this board.
i.e)
=> setmac 00:00:87:**:**:**

49
drivers/serial/serial_sh.c
View File

@ -20,14 +20,20 @@
#include <common.h>
#include <asm/processor.h>
#if defined (CONFIG_CONS_SCIF0)
#define SCIF_BASE SCIF0_BASE
#elif defined (CONFIG_CONS_SCIF1)
#define SCIF_BASE SCIF1_BASE
#elif defined (CONFIG_CONS_SCIF2)
#define SCIF_BASE SCIF2_BASE
#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE SCIF0_BASE
#elif defined(CONFIG_CONS_SCIF1)
# define SCIF_BASE SCIF1_BASE
#elif defined(CONFIG_CONS_SCIF2)
# define SCIF_BASE SCIF2_BASE
#elif defined(CONFIG_CONS_SCIF3)
# define SCIF_BASE SCIF3_BASE
#elif defined(CONFIG_CONS_SCIF4)
# define SCIF_BASE SCIF4_BASE
#elif defined(CONFIG_CONS_SCIF5)
# define SCIF_BASE SCIF5_BASE
#else
#error "Default SCIF doesn't set....."
# error "Default SCIF doesn't set....."
#endif
/* Base register */
@ -36,7 +42,8 @@
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
#if defined(CONFIG_CPU_SH7720) || \
(defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
@ -55,7 +62,7 @@
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
#elif defined(CONFIG_CPU_SH7763)
# if defined (CONFIG_CONS_SCIF2)
# if defined(CONFIG_CONS_SCIF2)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
@ -68,9 +75,20 @@
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
# endif
#elif defined(CONFIG_CPU_SH7723)
# if defined(CONIFG_SCIF_A)
# define SCLSR SCFSR
# define LSR_ORER 0x0200
# define FIFOLEVEL_MASK 0x3F
#else
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0x1F
#endif
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7722)
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7203)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
@ -89,6 +107,9 @@
/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
/* SH7723 SCIFA use bus clock. So clock *2 */
# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
#else /* Generic SuperH */
# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
@ -167,7 +188,7 @@ void serial_puts(const char *s)
int serial_tstc(void)
{
return serial_rx_fifo_level()? 1 : 0;
return serial_rx_fifo_level() ? 1 : 0;
}
#define FSR_ERR_CLEAR 0x0063
@ -191,14 +212,16 @@ int serial_getc_check(void)
handle_error();
if (*SCLSR & LSR_ORER)
handle_error();
return (status & (FSR_DR | FSR_RDF));
return status & (FSR_DR | FSR_RDF);
}
int serial_getc(void)
{
unsigned short status;
char ch;
while (!serial_getc_check()) ;
while (!serial_getc_check())
;
ch = *SCFRDR;
status = *SCFSR;

3
examples/Makefile
View File

@ -67,6 +67,9 @@ endif
ifeq ($(ARCH),sh)
LOAD_ADDR = 0x8C000000
ifeq ($(CPU),sh2)
BIG_ENDIAN=y
endif
endif
ifeq ($(ARCH),sparc)

40
include/asm-sh/cpu_sh2.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH2_H_
#define _ASM_CPU_SH2_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000008
#define CCR_CACHE_ENABLE 0x00000005
#define CCR_CACHE_ICI 0x00000008
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#define CACHE_OC_ENTRY_SHIFT 4
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
#else
# error "Unknown SH2 variant"
#endif
#endif /* _ASM_CPU_SH2_H_ */

4
include/asm-sh/cpu_sh4.h
View File

@ -35,10 +35,14 @@
# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
#elif defined (CONFIG_CPU_SH7785)
# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif

41
include/asm-sh/cpu_sh7203.h Normal file
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@ -0,0 +1,41 @@
#ifndef _ASM_CPU_SH7203_H_
#define _ASM_CPU_SH7203_H_
/* Cache */
#define CCR1 0xFFFC1000
#define CCR CCR1
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
/* SDRAM controller */
/* SCIF */
#define SCSMR_0 0xFFFE8000
#define SCIF0_BASE SCSMR_0
/* Timer(CMT) */
#define CMSTR 0xFFFEC000
#define CMCSR_0 0xFFFEC002
#define CMCNT_0 0xFFFEC004
#define CMCOR_0 0xFFFEC006
#define CMCSR_1 0xFFFEC008
#define CMCNT_1 0xFFFEC00A
#define CMCOR_1 0xFFFEC00C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7203_H_ */

209
include/asm-sh/cpu_sh7723.h Normal file
View File

@ -0,0 +1,209 @@
/*
* (C) Copyright 2008 Renesas Solutions Corp.
*
* SH7723 Internal I/O register
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH7723_H_
#define _ASM_CPU_SH7723_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* EXP */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* MMU */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* CACHE */
#define CCR 0xFF00001C
#define RAMCR 0xFF000074
/* INTC */
/* BSC */
#define CMNCR 0xFEC10000
#define CS0BCR 0xFEC10004
#define CS2BCR 0xFEC10008
#define CS4BCR 0xFEC10010
#define CS5ABCR 0xFEC10014
#define CS5BBCR 0xFEC10018
#define CS6ABCR 0xFEC1001C
#define CS6BBCR 0xFEC10020
#define CS0WCR 0xFEC10024
#define CS2WCR 0xFEC10028
#define CS4WCR 0xFEC10030
#define CS5AWCR 0xFEC10034
#define CS5BWCR 0xFEC10038
#define CS6AWCR 0xFEC1003C
#define CS6BWCR 0xFEC10040
#define RBWTCNT 0xFEC10054
/* SBSC */
#define SBSC_SDCR 0xFE400008
#define SBSC_SDWCR 0xFE40000C
#define SBSC_SDPCR 0xFE400010
#define SBSC_RTCSR 0xFE400014
#define SBSC_RTCNT 0xFE400018
#define SBSC_RTCOR 0xFE40001C
#define SBSC_RFCR 0xFE400020
/* DMAC */
/* CPG */
#define FRQCR 0xA4150000
#define VCLKCR 0xA4150004
#define SCLKACR 0xA4150008
#define SCLKBCR 0xA415000C
#define IRDACLKCR 0xA4150018
#define PLLCR 0xA4150024
#define DLLFRQ 0xA4150050
/* LOW POWER MODE */
#define STBCR 0xA4150020
#define MSTPCR0 0xA4150030
#define MSTPCR1 0xA4150034
#define MSTPCR2 0xA4150038
/* RWDT */
#define RWTCNT 0xA4520000
#define RWTCSR 0xA4520004
#define WTCNT RWTCNT
/* TMU */
#define TSTR 0xFFD80004
#define TCOR0 0xFFD80008
#define TCNT0 0xFFD8000C
#define TCR0 0xFFD80010
#define TCOR1 0xFFD80014
#define TCNT1 0xFFD80018
#define TCR1 0xFFD8001C
#define TCOR2 0xFFD80020
#define TCNT2 0xFFD80024
#define TCR2 0xFFD80028
/* TPU */
/* CMT */
#define CMSTR 0xA44A0000
#define CMCSR 0xA44A0060
#define CMCNT 0xA44A0064
#define CMCOR 0xA44A0068
/* MSIOF */
/* SCIF */
#define SCIF0_BASE 0xFFE00000
#define SCIF1_BASE 0xFFE10000
#define SCIF2_BASE 0xFFE20000
#define SCIF3_BASE 0xa4e30000
#define SCIF4_BASE 0xa4e40000
#define SCIF5_BASE 0xa4e50000
/* RTC */
/* IrDA */
/* KEYSC */
/* USB */
/* IIC */
/* FLCTL */
/* VPU */
/* VIO(CEU) */
/* VIO(VEU) */
/* VIO(BEU) */
/* 2DG */
/* LCDC */
/* VOU */
/* TSIF */
/* SIU */
/* ATAPI */
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PDCR 0xA4050106
#define PECR 0xA4050108
#define PFCR 0xA405010A
#define PGCR 0xA405010C
#define PHCR 0xA405010E
#define PJCR 0xA4050110
#define PKCR 0xA4050112
#define PLCR 0xA4050114
#define PMCR 0xA4050116
#define PNCR 0xA4050118
#define PQCR 0xA405011A
#define PRCR 0xA405011C
#define PSCR 0xA405011E
#define PTCR 0xA4050140
#define PUCR 0xA4050142
#define PVCR 0xA4050144
#define PWCR 0xA4050146
#define PXCR 0xA4050148
#define PYCR 0xA405014A
#define PZCR 0xA405014C
#define PSELA 0xA405014E
#define PSELB 0xA4050150
#define PSELC 0xA4050152
#define PSELD 0xA4050154
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
#define HIZCRD 0xA405015E
#define MSELCRA 0xA4050180
#define MSELCRB 0xA4050182
#define PULCR 0xA4050184
#define DRVCRA 0xA405018A
#define DRVCRB 0xA405018C
/* I/O Port */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
#define PDDR 0xA4050126
#define PEDR 0xA4050128
#define PFDR 0xA405012A
#define PGDR 0xA405012C
#define PHDR 0xA405012E
#define PJDR 0xA4050130
#define PKDR 0xA4050132
#define PLDR 0xA4050134
#define PMDR 0xA4050136
#define PNDR 0xA4050138
#define PQDR 0xA405013A
#define PRDR 0xA405013C
#define PSDR 0xA405013E
#define PTDR 0xA4050160
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
#define PYDR 0xA4050168
#define PZDR 0xA405016A
/* UBC */
/* H-UDI */
#endif /* _ASM_CPU_SH7723_H_ */

156
include/asm-sh/cpu_sh7785.h Normal file
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@ -0,0 +1,156 @@
#ifndef _ASM_CPU_SH7785_H_
#define _ASM_CPU_SH7785_H_
/*
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
* Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
/* Exceptions */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* Cache Controller */
#define CCR 0xFF00001C
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
#define RAMCR 0xFF000074
/* Watchdog Timer and Reset */
#define WTCNT WDTCNT
#define WDTST 0xFFCC0000
#define WDTCSR 0xFFCC0004
#define WDTBST 0xFFCC0008
#define WDTCNT 0xFFCC0010
#define WDTBCNT 0xFFCC0018
/* Timer Unit */
#define TSTR TSTR0
#define TOCR 0xFFD80000
#define TSTR0 0xFFD80004
#define TCOR0 0xFFD80008
#define TCNT0 0xFFD8000C
#define TCR0 0xFFD80010
#define TCOR1 0xFFD80014
#define TCNT1 0xFFD80018
#define TCR1 0xFFD8001C
#define TCOR2 0xFFD80020
#define TCNT2 0xFFD80024
#define TCR2 0xFFD80028
#define TCPR2 0xFFD8002C
#define TSTR1 0xFFDC0004
#define TCOR3 0xFFDC0008
#define TCNT3 0xFFDC000C
#define TCR3 0xFFDC0010
#define TCOR4 0xFFDC0014
#define TCNT4 0xFFDC0018
#define TCR4 0xFFDC001C
#define TCOR5 0xFFDC0020
#define TCNT5 0xFFDC0024
#define TCR5 0xFFDC0028
/* Serial Communication Interface with FIFO */
#define SCIF1_BASE 0xffeb0000
/* LBSC */
#define MMSELR 0xfc400020
#define LBSC_BASE 0xff800000
#define BCR (LBSC_BASE + 0x1000)
#define CS0BCR (LBSC_BASE + 0x2000)
#define CS1BCR (LBSC_BASE + 0x2010)
#define CS2BCR (LBSC_BASE + 0x2020)
#define CS3BCR (LBSC_BASE + 0x2030)
#define CS4BCR (LBSC_BASE + 0x2040)
#define CS5BCR (LBSC_BASE + 0x2050)
#define CS6BCR (LBSC_BASE + 0x2060)
#define CS0WCR (LBSC_BASE + 0x2008)
#define CS1WCR (LBSC_BASE + 0x2018)
#define CS2WCR (LBSC_BASE + 0x2028)
#define CS3WCR (LBSC_BASE + 0x2038)
#define CS4WCR (LBSC_BASE + 0x2048)
#define CS5WCR (LBSC_BASE + 0x2058)
#define CS6WCR (LBSC_BASE + 0x2068)
#define CS5PCR (LBSC_BASE + 0x2070)
#define CS6PCR (LBSC_BASE + 0x2080)
/* PCI Controller */
#define SH7780_PCIECR 0xFE000008
#define SH7780_PCIVID 0xFE040000
#define SH7780_PCIDID 0xFE040002
#define SH7780_PCICMD 0xFE040004
#define SH7780_PCISTATUS 0xFE040006
#define SH7780_PCIRID 0xFE040008
#define SH7780_PCIPIF 0xFE040009
#define SH7780_PCISUB 0xFE04000A
#define SH7780_PCIBCC 0xFE04000B
#define SH7780_PCICLS 0xFE04000C
#define SH7780_PCILTM 0xFE04000D
#define SH7780_PCIHDR 0xFE04000E
#define SH7780_PCIBIST 0xFE04000F
#define SH7780_PCIIBAR 0xFE040010
#define SH7780_PCIMBAR0 0xFE040014
#define SH7780_PCIMBAR1 0xFE040018
#define SH7780_PCISVID 0xFE04002C
#define SH7780_PCISID 0xFE04002E
#define SH7780_PCICP 0xFE040034
#define SH7780_PCIINTLINE 0xFE04003C
#define SH7780_PCIINTPIN 0xFE04003D
#define SH7780_PCIMINGNT 0xFE04003E
#define SH7780_PCIMAXLAT 0xFE04003F
#define SH7780_PCICID 0xFE040040
#define SH7780_PCINIP 0xFE040041
#define SH7780_PCIPMC 0xFE040042
#define SH7780_PCIPMCSR 0xFE040044
#define SH7780_PCIPMCSRBSE 0xFE040046
#define SH7780_PCI_CDD 0xFE040047
#define SH7780_PCICR 0xFE040100
#define SH7780_PCILSR0 0xFE040104
#define SH7780_PCILSR1 0xFE040108
#define SH7780_PCILAR0 0xFE04010C
#define SH7780_PCILAR1 0xFE040110
#define SH7780_PCIIR 0xFE040114
#define SH7780_PCIIMR 0xFE040118
#define SH7780_PCIAIR 0xFE04011C
#define SH7780_PCICIR 0xFE040120
#define SH7780_PCIAINT 0xFE040130
#define SH7780_PCIAINTM 0xFE040134
#define SH7780_PCIBMIR 0xFE040138
#define SH7780_PCIPAR 0xFE0401C0
#define SH7780_PCIPINT 0xFE0401CC
#define SH7780_PCIPINTM 0xFE0401D0
#define SH7780_PCIMBR0 0xFE0401E0
#define SH7780_PCIMBMR0 0xFE0401E4
#define SH7780_PCIMBR1 0xFE0401E8
#define SH7780_PCIMBMR1 0xFE0401EC
#define SH7780_PCIMBR2 0xFE0401F0
#define SH7780_PCIMBMR2 0xFE0401F4
#define SH7780_PCIIOBR 0xFE0401F8
#define SH7780_PCIIOBMR 0xFE0401FC
#define SH7780_PCICSCR0 0xFE040210
#define SH7780_PCICSCR1 0xFE040214
#define SH7780_PCICSAR0 0xFE040218
#define SH7780_PCICSAR1 0xFE04021C
#define SH7780_PCIPDR 0xFE040220
#endif /* _ASM_CPU_SH7780_H_ */

5
include/asm-sh/processor.h
View File

@ -1,6 +1,9 @@
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
#if defined CONFIG_SH3
#if defined(CONFIG_SH2) || \
defined (CONFIG_SH2A)
# include <asm/cpu_sh2.h>
#elif defined (CONFIG_SH3)
# include <asm/cpu_sh3.h>
#elif defined (CONFIG_SH4) || \
defined (CONFIG_SH4A)

177
include/configs/ap325rxa.h Normal file
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@ -0,0 +1,177 @@
/*
* Configuation settings for the Renesas Solutions AP-325RXA board
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __AP325RXA_H
#define __AP325RXA_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7723 1
#define CONFIG_AP325RXA 1
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC2,38400"
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_32_BIT 1
#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
/* MEMORY */
#define AP325RXA_SDRAM_BASE (0x88000000)
#define AP325RXA_FLASH_BASE_1 (0xA0000000)
#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
/* undef to save memory */
#define CFG_LONGHELP
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
/* Buffer size for input from the Console */
#define CFG_CBSIZE 256
/* Buffer size for Console output */
#define CFG_PBSIZE 256
/* max args accepted for monitor commands */
#define CFG_MAXARGS 16
/* Buffer size for Boot Arguments passed to kernel */
#define CFG_BARGSIZE 512
/* List of legal baudrate settings for this board */
#define CFG_BAUDRATE_TABLE { 38400 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
#define CONFIG_CONS_SCIF5 1
/* Suppress display of console information at boot */
#undef CFG_CONSOLE_INFO_QUIET
#undef CFG_CONSOLE_OVERWRITE_ROUTINE
#undef CFG_CONSOLE_ENV_OVERWRITE
#define CFG_MEMTEST_START (AP325RXA_SDRAM_BASE)
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
/* Enable alternate, more extensive, memory test */
#undef CFG_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CFG_MEMTEST_SCRATCH
/* Enable temporary baudrate change while serial download */
#undef CFG_LOADS_BAUD_CHANGE
#define CFG_SDRAM_BASE (AP325RXA_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CFG_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
/* Monitor size */
#define CFG_MONITOR_LEN (128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CFG_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CFG_FLASH_BASE (AP325RXA_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CFG_MAX_FLASH_SECT 512
/*
* IDE support
*/
#define CONFIG_IDE_RESET 1
#define CFG_PIO_MODE 1
#define CFG_IDE_MAXBUS 1 /* IDE bus */
#define CFG_IDE_MAXDEVICE 1
#define CFG_ATA_BASE_ADDR 0xB4180000
#define CFG_ATA_STRIDE 2 /* 1bit shift */
#define CFG_ATA_DATA_OFFSET 0x200 /* data reg offset */
#define CFG_ATA_REG_OFFSET 0x200 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x210 /* alternate register offset */
/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
/* Timeout for Flash erase operations (in ms) */
#define CFG_FLASH_ERASE_TOUT (3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CFG_FLASH_WRITE_TOUT (3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CFG_FLASH_LOCK_TOUT (3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
/*
* Use hardware flash sectors protection instead
* of U-Boot software protection
*/
#undef CFG_FLASH_PROTECTION
#undef CFG_DIRECT_FLASH_TFTP
/* ENV setting */
#define CFG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CFG_ENV_SECT_SIZE (128 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/* Offset of env Flash sector relative to CFG_FLASH_BASE */
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#endif /* __AP325RXA_H */

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/*
* Configuation settings for the Renesas Technology RSK 7203
*
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __RSK7203_H
#define __RSK7203_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH2 1
#define CONFIG_SH2A 1
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define RSK7203_SDRAM_BASE 0x0C000000
#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
#define CFG_PBSIZE 256 /* Buffer size for Console output */
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
/* Buffer size for Boot Arguments passed to kernel */
#define CFG_BARGSIZE 512
/* List of legal baudrate settings for this board */
#define CFG_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CFG_MEMTEST_START RSK7203_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (3 * 1024 * 1024))
#define CFG_SDRAM_BASE RSK7203_SDRAM_BASE
#define CFG_SDRAM_SIZE (32 * 1024 * 1024)
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 1024 * 1024)
#define CFG_MONITOR_BASE RSK7203_FLASH_BASE_1
#define CFG_MONITOR_LEN (128 * 1024)
#define CFG_MALLOC_LEN (256 * 1024)
#define CFG_GBL_DATA_SIZE 256
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_BASE RSK7203_FLASH_BASE_1
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_SECT 64
#define CFG_MAX_FLASH_BANKS 1
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE (64 * 1024)
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 12000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
#endif /* __RSK7203_H */

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/*
* Configuation settings for the Renesas Technology R0P7785LC0011RL board
*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SH7785LCR_H
#define __SH7785LCR_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4A 1
#define CONFIG_CPU_SH7785 1
#define CONFIG_SH7785LCR 1
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ENV
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevice=0:1\0" \
"usbload=usb reset;usbboot;usb stop;bootm\0"
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7785LCR_SDRAM_BASE (0x08000000)
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xb4000000)
#define CFG_LONGHELP
#define CFG_PROMPT "=> "
#define CFG_CBSIZE 256
#define CFG_PBSIZE 256
#define CFG_MAXARGS 16
#define CFG_BARGSIZE 512
#define CFG_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_SCIF_EXT_CLOCK 1
#undef CFG_CONSOLE_INFO_QUIET
#undef CFG_CONSOLE_OVERWRITE_ROUTINE
#undef CFG_CONSOLE_ENV_OVERWRITE
#define CFG_MEMTEST_START (SH7785LCR_SDRAM_BASE)
#define CFG_MEMTEST_END (CFG_MEMTEST_START + \
(SH7785LCR_SDRAM_SIZE) - \
4 * 1024 * 1024)
#undef CFG_ALT_MEMTEST
#undef CFG_MEMTEST_SCRATCH
#undef CFG_LOADS_BAUD_CHANGE
#define CFG_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
#define CFG_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
#define CFG_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
#define CFG_MONITOR_LEN (512 * 1024)
#define CFG_MALLOC_LEN (512 * 1024)
#define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
#define CFG_MAX_FLASH_SECT 512
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + \
(0 * SH7785LCR_FLASH_BANK_SIZE) }
#define CFG_FLASH_ERASE_TOUT (3 * 1000)
#define CFG_FLASH_WRITE_TOUT (3 * 1000)
#define CFG_FLASH_LOCK_TOUT (3 * 1000)
#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
#undef CFG_FLASH_PROTECTION
#undef CFG_DIRECT_FLASH_TFTP
/* R8A66597 */
#define LITTLEENDIAN /* for include/usb.h */
#define CONFIG_USB_R8A66597_HCD
#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
/* PCI Controller */
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
/* Network device (RTL8169) support */
#define CONFIG_NET_MULTI
#define CONFIG_RTL8169
/* ENV setting */
#define CFG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CFG_ENV_SECT_SIZE (256 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
#define TMU_CLK_DIVIDER 4
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#endif /* __SH7785LCR_H */