4xx: Remove binary cpld bitstream from DP405 board
This patch removes the cpld binary bitstream that is used by esd's cpld command on DP405 boards. Because u-boot with an external cpld bitstream may not take more space in flash than before the u-boot binary is shrinked a little bit. Some unused featues have been removed therefore. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Wolfgang Denk
parent
700d553fd3
commit
de47a34d4d
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@ -21,9 +21,4 @@
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# MA 02111-1307 USA
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#
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#
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# esd VOH405 boards
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#
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TEXT_BASE = 0xFFFC0000
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#TEXT_BASE = 0x00FC0000
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TEXT_BASE = 0xFFFD0000
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@ -29,14 +29,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* fpga configuration data - not compressed, generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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int filesize = sizeof(fpgadata);
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int board_early_init_f (void)
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{
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/*
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File diff suppressed because it is too large
Load Diff
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@ -52,39 +52,20 @@
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_CMD_NET
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
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#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */
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@ -134,33 +115,6 @@
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
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#undef CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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@ -191,21 +145,16 @@
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#if 0 /* test-only */
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
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#endif
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
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# define CONFIG_SYS_RAMBOOT 1
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@ -221,9 +170,6 @@
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#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
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/* total size of a CAT24WC16 is 2048 bytes */
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment
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*/
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@ -245,18 +191,11 @@
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*/
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#define CAN_BA 0xF0000000 /* CAN Base Address */
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#define RTC_BA 0xF0000500 /* RTC Base Address */
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x92015480
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#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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#if 0 /* test-only */
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x92015480
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#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
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#endif
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/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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@ -264,9 +203,6 @@
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/*-----------------------------------------------------------------------
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* FPGA stuff
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*/
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#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
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#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
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/* FPGA program pin configuration */
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#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
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#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
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@ -312,7 +248,7 @@
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#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
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#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
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#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
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/*
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* Internal Definitions
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@ -326,17 +262,7 @@
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* This value will be set if iic boot eprom is disabled.
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*/
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
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#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
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#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
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#endif
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#if 1
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#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
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#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
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#endif
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#endif /* __CONFIG_H */
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