imx: imx-common: introduce Resource Domain Controller support
Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
613e01065a
commit
de09c43bbf
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@ -3,3 +3,11 @@ config IMX_CONFIG
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config ROM_UNIFIED_SECTIONS
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bool
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config IMX_RDC
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bool "i.MX Resource domain controller driver"
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depends on ARCH_MX6 || ARCH_MX7
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help
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i.MX Resource domain controller is used to assign masters
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and peripherals to differet domains. This can be used to
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isolate resources.
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@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
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obj-y += cache.o init.o
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obj-$(CONFIG_CMD_SATA) += sata.o
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obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
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obj-$(CONFIG_IMX_RDC) += rdc-sema.o
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obj-$(CONFIG_SECURE_BOOT) += hab.o
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endif
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ifeq ($(SOC),$(filter $(SOC),vf610))
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@ -0,0 +1,183 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/imx-common/rdc-sema.h>
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#include <asm/arch/imx-rdc.h>
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#include <asm-generic/errno.h>
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/*
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* Check if the RDC Semaphore is required for this peripheral.
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*/
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static inline int imx_rdc_check_sema_required(int per_id)
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{
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struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
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u32 reg;
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reg = readl(&imx_rdc->pdap[per_id]);
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/*
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* No semaphore:
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* Intial value or this peripheral is assigned to only one domain
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*/
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if (!(reg & RDC_PDAP_SREQ_MASK))
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return -ENOENT;
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return 0;
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}
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/*
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* Check the peripheral read / write access permission on Domain [dom_id].
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*/
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int imx_rdc_check_permission(int per_id, int dom_id)
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{
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struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
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u32 reg;
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reg = readl(&imx_rdc->pdap[per_id]);
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if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
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return -EACCES; /*No access*/
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return 0;
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}
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/*
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* Lock up the RDC semaphore for this peripheral if semaphore is required.
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*/
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int imx_rdc_sema_lock(int per_id)
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{
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struct rdc_sema_regs *imx_rdc_sema;
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int ret;
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u8 reg;
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ret = imx_rdc_check_sema_required(per_id);
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if (ret)
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return ret;
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if (per_id < SEMA_GATES_NUM)
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imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
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else
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imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
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do {
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writeb(RDC_SEMA_PROC_ID,
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&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
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reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
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if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
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break; /* Get the Semaphore*/
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} while (1);
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return 0;
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}
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/*
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* Unlock the RDC semaphore for this peripheral if main CPU is the
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* semaphore owner.
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*/
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int imx_rdc_sema_unlock(int per_id)
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{
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struct rdc_sema_regs *imx_rdc_sema;
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int ret;
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u8 reg;
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ret = imx_rdc_check_sema_required(per_id);
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if (ret)
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return ret;
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if (per_id < SEMA_GATES_NUM)
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imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
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else
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imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
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reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
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if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
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return 1; /*Not the semaphore owner */
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writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
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return 0;
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}
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/*
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* Setup RDC setting for one peripheral
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*/
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int imx_rdc_setup_peri(rdc_peri_cfg_t p)
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{
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struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
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u32 reg = 0;
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u32 share_count = 0;
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u32 peri_id = p & RDC_PERI_MASK;
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u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
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/* No domain assigned */
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if (domain == 0)
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return -EINVAL;
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reg |= domain;
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share_count = (domain & 0x3)
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+ ((domain >> 2) & 0x3)
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+ ((domain >> 4) & 0x3)
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+ ((domain >> 6) & 0x3);
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if (share_count > 0x3)
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reg |= RDC_PDAP_SREQ_MASK;
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writel(reg, &imx_rdc->pdap[peri_id]);
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return 0;
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}
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/*
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* Setup RDC settings for multiple peripherals
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*/
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int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
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unsigned count)
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{
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rdc_peri_cfg_t const *p = peripherals_list;
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int i, ret;
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for (i = 0; i < count; i++) {
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ret = imx_rdc_setup_peri(*p);
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if (ret)
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return ret;
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p++;
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}
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return 0;
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}
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/*
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* Setup RDC setting for one master
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*/
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int imx_rdc_setup_ma(rdc_ma_cfg_t p)
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{
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struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
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u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
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u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
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writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
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return 0;
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}
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/*
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* Setup RDC settings for multiple masters
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*/
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int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
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{
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rdc_ma_cfg_t const *p = masters_list;
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int i, ret;
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for (i = 0; i < count; i++) {
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ret = imx_rdc_setup_ma(*p);
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if (ret)
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return ret;
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p++;
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}
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return 0;
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}
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@ -0,0 +1,12 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __IMX_RDC_H__
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#define __IMX_RDC_H__
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#error "Please select cpu"
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#endif /* __IMX_RDC_H__*/
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@ -0,0 +1,100 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __RDC_SEMA_H__
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#define __RDC_SEMA_H__
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/*
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* rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
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*
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* [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
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* d3 d2 d1 d0 | master id | peri id
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* d[x] means domain[x], x can be [3 - 0].
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*/
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typedef u32 rdc_peri_cfg_t;
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typedef u32 rdc_ma_cfg_t;
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#define RDC_PERI_SHIFT 0
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#define RDC_PERI_MASK 0xFF
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#define RDC_DOMAIN_SHIFT_BASE 16
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#define RDC_DOMAIN_MASK 0xFF0000
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#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
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#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
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#define RDC_MASTER_SHIFT 8
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#define RDC_MASTER_MASK 0xFF00
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#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
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(domain_id << RDC_DOMAIN_SHIFT_BASE))
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/* The Following macro definitions are common to i.MX6SX and i.MX7D */
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#define SEMA_GATES_NUM 64
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#define RDC_MDA_DID_SHIFT 0
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#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
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#define RDC_MDA_LCK_SHIFT 31
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#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
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#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
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#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
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#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
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#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
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#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
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RDC_PDAP_DR_MASK(domain))
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#define RDC_PDAP_SREQ_SHIFT 30
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#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
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#define RDC_PDAP_LCK_SHIFT 31
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#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
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#define RDC_MRSA_SADR_SHIFT 7
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#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
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#define RDC_MREA_EADR_SHIFT 7
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#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
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#define RDC_MRC_DW_SHIFT(domain) (domain)
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#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
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#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
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#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
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#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
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RDC_MRC_DR_MASK(domain))
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#define RDC_MRC_ENA_SHIFT 30
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#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
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#define RDC_MRC_LCK_SHIFT 31
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#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
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#define RDC_MRVS_VDID_SHIFT 0
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#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
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#define RDC_MRVS_AD_SHIFT 4
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#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
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#define RDC_MRVS_VADDR_SHIFT 5
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#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
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#define RDC_SEMA_GATE_GTFSM_SHIFT 0
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#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
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#define RDC_SEMA_GATE_LDOM_SHIFT 5
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#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
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#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
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#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
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#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
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#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
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int imx_rdc_check_permission(int per_id, int dom_id);
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int imx_rdc_sema_lock(int per_id);
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int imx_rdc_sema_unlock(int per_id);
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int imx_rdc_setup_peri(rdc_peri_cfg_t p);
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int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
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unsigned count);
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int imx_rdc_setup_ma(rdc_ma_cfg_t p);
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int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
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#endif /* __RDC_SEMA_H__*/
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