Merge with /home/hs/jupiter/u-boot
This commit is contained in:
Wolfgang Denk
Wolfgang Denk
commit
dd0321f5f8
3
Makefile
3
Makefile
|
|
@ -412,6 +412,9 @@ icecube_5100_config: unconfig
|
|||
}
|
||||
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
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||||
|
||||
jupiter_config: unconfig
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||||
@$(MKCONFIG) jupiter ppc mpc5xxx jupiter
|
||||
|
||||
v38b_config: unconfig
|
||||
@./mkconfig -a v38b ppc mpc5xxx v38b
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||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
|
||||
#
|
||||
# (C) Copyright 2003-2006
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||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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||||
# MA 02111-1307 USA
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||||
#
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||||
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include $(TOPDIR)/config.mk
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||||
LIB = $(obj)lib$(BOARD).a
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||||
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||||
COBJS := $(BOARD).o
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||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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||||
OBJS := $(addprefix $(obj),$(COBJS))
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||||
SOBJS := $(addprefix $(obj),$(SOBJS))
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||||
|
||||
$(LIB): $(obj).depend $(OBJS)
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||||
$(AR) $(ARFLAGS) $@ $(OBJS)
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||||
|
||||
clean:
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||||
rm -f $(SOBJS) $(OBJS)
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||||
|
||||
distclean: clean
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||||
rm -f $(LIB) core *.bak .depend
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||||
|
||||
#########################################################################
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||||
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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||||
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sinclude $(obj).depend
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||||
|
||||
#########################################################################
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|
@ -0,0 +1,41 @@
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|||
#
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||||
# (C) Copyright 2007
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||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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||||
# Jupiter board:
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#
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# Valid values for TEXT_BASE are:
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#
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||||
# 0xFFF00000 boot high (standard configuration)
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# 0x00100000 boot from RAM (for testing only)
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#
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ifndef TEXT_BASE
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## Standard: boot high
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TEXT_BASE = 0xFFF00000
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## For testing: boot from RAM
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||||
# TEXT_BASE = 0x00100000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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#PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -DDEBUG -I$(TOPDIR)/board
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@ -0,0 +1,317 @@
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/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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||||
*
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||||
* (C) Copyright 2004
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||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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||||
*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <asm/processor.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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||||
#endif
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||||
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||||
#define SDRAM_DDR 0
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||||
#if 1
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||||
/* Settings Icecube */
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||||
#define SDRAM_MODE 0x00CD0000
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#define SDRAM_CONTROL 0x504F0000
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#define SDRAM_CONFIG1 0xD2322800
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#define SDRAM_CONFIG2 0x8AD70000
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#else
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/*Settings Jupiter UB 1.0.0 */
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#define SDRAM_MODE 0x008D0000
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#define SDRAM_CONTROL 0xD04F0000
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#define SDRAM_CONFIG1 0xf7277f00
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#define SDRAM_CONFIG2 0x88b70004
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#endif
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||||
#ifndef CFG_RAMBOOT
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||||
static void sdram_start (int hi_addr)
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||||
{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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||||
/* unlock mode register */
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||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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||||
#if SDRAM_DDR
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||||
/* set mode register: extended mode */
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||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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||||
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||||
/* set mode register: reset DLL */
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||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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||||
__asm__ volatile ("sync");
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||||
#endif
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||||
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||||
/* precharge all banks */
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||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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||||
__asm__ volatile ("sync");
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||||
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||||
/* auto refresh */
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||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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||||
__asm__ volatile ("sync");
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||||
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||||
/* set mode register */
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||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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||||
__asm__ volatile ("sync");
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||||
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||||
/* normal operation */
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||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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||||
__asm__ volatile ("sync");
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||||
}
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||||
#endif
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||||
|
||||
/*
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||||
* ATTENTION: Although partially referenced initdram does NOT make real use
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||||
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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||||
* is something else than 0x00000000.
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||||
*/
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||||
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||||
long int initdram (int board_type)
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||||
{
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||||
ulong dramsize = 0;
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||||
ulong dramsize2 = 0;
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||||
uint svr, pvr;
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||||
|
||||
#ifndef CFG_RAMBOOT
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||||
ulong test1, test2;
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||||
|
||||
/* setup SDRAM chip selects */
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||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
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||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
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||||
__asm__ volatile ("sync");
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||||
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||||
/* setup config registers */
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||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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||||
__asm__ volatile ("sync");
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||||
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||||
#if SDRAM_DDR
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||||
/* set tap delay */
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||||
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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||||
__asm__ volatile ("sync");
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||||
#endif
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||||
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||||
/* find RAM size using SDRAM CS0 only */
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||||
sdram_start(0);
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||||
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
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||||
sdram_start(1);
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||||
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
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||||
if (test1 > test2) {
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||||
sdram_start(0);
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||||
dramsize = test1;
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||||
} else {
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||||
dramsize = test2;
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||||
}
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||||
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||||
/* memory smaller than 1MB is impossible */
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||||
if (dramsize < (1 << 20)) {
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||||
dramsize = 0;
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||||
}
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||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */
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||||
if (dramsize > 0) {
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||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
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||||
} else {
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||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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||||
}
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||||
|
||||
/* let SDRAM CS1 start right after CS0 */
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||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
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||||
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||||
/* find RAM size using SDRAM CS1 only */
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||||
if (!dramsize)
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||||
sdram_start(0);
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||||
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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||||
if (!dramsize) {
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||||
sdram_start(1);
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||||
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
|
||||
}
|
||||
if (test1 > test2) {
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||||
sdram_start(0);
|
||||
dramsize2 = test1;
|
||||
} else {
|
||||
dramsize2 = test2;
|
||||
}
|
||||
|
||||
/* memory smaller than 1MB is impossible */
|
||||
if (dramsize2 < (1 << 20)) {
|
||||
dramsize2 = 0;
|
||||
}
|
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */
|
||||
if (dramsize2 > 0) {
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
|
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
|
||||
} else {
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
||||
}
|
||||
|
||||
#else /* CFG_RAMBOOT */
|
||||
|
||||
/* retrieve size of memory connected to SDRAM CS0 */
|
||||
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
|
||||
if (dramsize >= 0x13) {
|
||||
dramsize = (1 << (dramsize - 0x13)) << 20;
|
||||
} else {
|
||||
dramsize = 0;
|
||||
}
|
||||
|
||||
/* retrieve size of memory connected to SDRAM CS1 */
|
||||
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
|
||||
if (dramsize2 >= 0x13) {
|
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
||||
} else {
|
||||
dramsize2 = 0;
|
||||
}
|
||||
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/*
|
||||
* On MPC5200B we need to set the special configuration delay in the
|
||||
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
|
||||
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
|
||||
*
|
||||
* "The SDelay should be written to a value of 0x00000004. It is
|
||||
* required to account for changes caused by normal wafer processing
|
||||
* parameters."
|
||||
*/
|
||||
svr = get_svr();
|
||||
pvr = get_pvr();
|
||||
if ((SVR_MJREV(svr) >= 2) &&
|
||||
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
|
||||
|
||||
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
return dramsize + dramsize2;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: Sauter (Jupiter)\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flash_preinit(void)
|
||||
{
|
||||
/*
|
||||
* Now, when we are in RAM, enable flash write
|
||||
* access for detection process.
|
||||
* Note that CS_BOOT cannot be cleared when
|
||||
* executing in flash.
|
||||
*/
|
||||
#if defined(CONFIG_MGT5100)
|
||||
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
|
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
|
||||
#endif
|
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
}
|
||||
|
||||
int board_early_init_r (void)
|
||||
{
|
||||
flash_preinit ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flash_afterinit(ulong size)
|
||||
{
|
||||
if (size == 0x1000000) { /* adjust mapping */
|
||||
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
|
||||
START_REG(CFG_BOOTCS_START | size);
|
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
|
||||
STOP_REG(CFG_BOOTCS_START | size, size);
|
||||
}
|
||||
#if defined(CONFIG_MPC5200)
|
||||
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
|
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
|
||||
#endif
|
||||
}
|
||||
|
||||
int update_flash_size (int flash_size)
|
||||
{
|
||||
flash_afterinit (flash_size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
||||
|
||||
void init_ide_reset (void)
|
||||
{
|
||||
debug ("init_ide_reset\n");
|
||||
|
||||
/* Configure PSC1_4 as GPIO output for ATA reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
|
||||
/* Deassert reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
|
||||
}
|
||||
|
||||
void ide_set_reset (int idereset)
|
||||
{
|
||||
debug ("ide_reset(%d)\n", idereset);
|
||||
|
||||
if (idereset) {
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
|
||||
/* Make a delay. MPC5200 spec says 25 usec min */
|
||||
udelay(500000);
|
||||
} else {
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
|
||||
}
|
||||
}
|
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc5xxx/start.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -878,12 +878,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
|||
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
|
||||
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
||||
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
||||
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
|
||||
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
|
||||
defined(CONFIG_MCC200) || defined(CONFIG_MOTIONPRO) || \
|
||||
defined(CONFIG_O2DNT) || defined(CONFIG_PM520) || \
|
||||
defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200) || \
|
||||
defined(CONFIG_UC101) || defined(CONFIG_V38B)
|
||||
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
|
||||
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
|
||||
defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \
|
||||
defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \
|
||||
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
|
||||
defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \
|
||||
defined(CONFIG_V38B)
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
fec->xcv_type = MII100;
|
||||
# else
|
||||
|
|
|
|||
|
|
@ -0,0 +1,277 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_MPC5200 1 /* especially an MPC5200 */
|
||||
#define CONFIG_JUPITER 1 /* ... on Jupiter board */
|
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* PCI Mapping:
|
||||
* 0x40000000 - 0x4fffffff - PCI Memory
|
||||
* 0x50000000 - 0x50ffffff - PCI IO Space
|
||||
*/
|
||||
//#define CONFIG_PCI
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_PCI_PNP 1
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||
#define ADD_PCI_CMD CFG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#define CFG_XLB_PIPELINING 1
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_MII 1
|
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/jupiter/uImage\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||
|
||||
#if 0
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,5200@0"
|
||||
#define OF_SOC "soc5200@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFF000000
|
||||
#define CFG_FLASH_SIZE 0x01000000
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
|
||||
#define CFG_UPDATE_FLASH_SIZE 1
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xF0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
/*
|
||||
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
|
||||
*/
|
||||
/* #define CONFIG_FEC_10MBIT 1 */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define CFG_GPS_PORT_CONFIG 0x10000004
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
#define CFG_ALT_MEMTEST 1
|
||||
|
||||
#define CFG_LOAD_ADDR 0x200000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#define CFG_BOOTCS_CFG 0x00047801
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333333
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue