TQM860M: Support for 10col SDRAMs, max. 128 MiB
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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@ -368,7 +368,7 @@
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*/
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*/
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#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
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#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
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#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CFG_OR_TIMING_SDRAM 0x00000A00
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#define CFG_OR_TIMING_SDRAM 0x00000A00
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@ -444,7 +444,10 @@
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/* 10 column SDRAM */
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#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/*
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/*
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* Internal Definitions
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* Internal Definitions
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