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MIPS: mips32/cache.S: remove superfluous register assignment 

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
This commit is contained in:
Gabor Juhos 2013-06-12 18:02:46 +02:00 committed by Tom Rini
parent b1a14c471c
commit da84f33b04
1 changed files with 1 additions and 2 deletions
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3
arch/mips/cpu/mips32/cache.S
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@ -129,7 +129,6 @@ NESTED(mips_cache_reset, 0, ra)
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
@ -164,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
* then initialize D-cache.
*/
move a1, t3
move a2, t5
move a2, t4
PTR_LA t7, mips_init_dcache
jalr t7