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zynq: sdhci: Move driver to DM 

Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Michal Simek 2015-11-30 16:13:03 +01:00
parent 400434537b
commit d9ae52c8f0
9 changed files with 37 additions and 59 deletions
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2
arch/arm/Kconfig
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@ -553,6 +553,7 @@ config ARCH_ZYNQ
select DM select DM
select DM_ETH select DM_ETH
select SPL_DM select SPL_DM
select DM_MMC
select DM_SPI select DM_SPI
select DM_SERIAL select DM_SERIAL
select DM_SPI_FLASH select DM_SPI_FLASH
@ -564,6 +565,7 @@ config ARCH_ZYNQMP
select DM select DM
select OF_CONTROL select OF_CONTROL
select DM_ETH select DM_ETH
select DM_MMC
select DM_SERIAL select DM_SERIAL
config TEGRA config TEGRA

3
arch/arm/dts/zynq-zc702.dts
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@ -18,6 +18,7 @@
i2c0 = &i2c0; i2c0 = &i2c0;
serial0 = &uart1; serial0 = &uart1;
spi0 = &qspi; spi0 = &qspi;
mmc0 = &sdhci0;
}; };
memory { memory {
@ -370,6 +371,7 @@
}; };
&sdhci0 { &sdhci0 {
u-boot,dm-pre-reloc;
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>; pinctrl-0 = <&pinctrl_sdhci0_default>;
@ -383,6 +385,7 @@
}; };
&qspi { &qspi {
u-boot,dm-pre-reloc;
status = "okay"; status = "okay";
}; };

3
arch/arm/include/asm/arch-zynqmp/hardware.h
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@ -19,9 +19,6 @@
#define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR0 0xFF020000
#define ZYNQ_I2C_BASEADDR1 0xFF030000 #define ZYNQ_I2C_BASEADDR1 0xFF030000
#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
#define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000

1
arch/arm/include/asm/arch-zynqmp/sys_proto.h
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@ -13,7 +13,6 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{ {
} }
int zynq_sdhci_init(phys_addr_t regbase);
int zynq_slcr_get_mio_pin_status(const char *periph); int zynq_slcr_get_mio_pin_status(const char *periph);
unsigned int zynqmp_get_silicon_version(void); unsigned int zynqmp_get_silicon_version(void);

2
arch/arm/mach-zynq/include/mach/hardware.h
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@ -12,8 +12,6 @@
#define ZYNQ_SCU_BASEADDR 0xF8F00000 #define ZYNQ_SCU_BASEADDR 0xF8F00000
#define ZYNQ_GEM_BASEADDR0 0xE000B000 #define ZYNQ_GEM_BASEADDR0 0xE000B000
#define ZYNQ_GEM_BASEADDR1 0xE000C000 #define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR0 0xE0006000

2
arch/arm/mach-zynq/include/mach/sys_proto.h
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@ -20,8 +20,6 @@ extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void); extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */ /* Driver extern functions */
extern int zynq_sdhci_init(phys_addr_t regbase);
extern void ps7_init(void); extern void ps7_init(void);
#endif /* _SYS_PROTO_H_ */ #endif /* _SYS_PROTO_H_ */

17
board/xilinx/zynq/board.c
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@ -122,23 +122,6 @@ int board_eth_init(bd_t *bis)
return ret; return ret;
} }
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
int ret = 0;
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
return ret;
}
#endif
int dram_init(void) int dram_init(void)
{ {
#if CONFIG_IS_ENABLED(OF_CONTROL) #if CONFIG_IS_ENABLED(OF_CONTROL)

22
board/xilinx/zynqmp/zynqmp.c
View File

@ -65,28 +65,6 @@ void scsi_init(void)
} }
#endif #endif
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
int ret = 0;
u32 ver = zynqmp_get_silicon_version();
if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
}
return ret;
}
#endif
int board_late_init(void) int board_late_init(void)
{ {
u32 reg = 0; u32 reg = 0;

44
drivers/mmc/zynq_sdhci.c
View File

@ -1,5 +1,5 @@
/* /*
* (C) Copyright 2013 Inc. * (C) Copyright 2013 - 2015 Xilinx, Inc.
* *
* Xilinx Zynq SD Host Controller Interface * Xilinx Zynq SD Host Controller Interface
* *
@ -7,28 +7,48 @@
*/ */
#include <common.h> #include <common.h>
#include <dm.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <libfdt.h> #include <libfdt.h>
#include <malloc.h> #include <malloc.h>
#include <sdhci.h> #include <sdhci.h>
#include <asm/arch/sys_proto.h>
int zynq_sdhci_init(phys_addr_t regbase) static int arasan_sdhci_probe(struct udevice *dev)
{ {
struct sdhci_host *host = NULL; struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("zynq_sdhci_init: sdhci_host malloc fail\n");
return 1;
}
host->name = "zynq_sdhci";
host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B; SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0); add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0);
upriv->mmc = host->mmc;
return 0; return 0;
} }
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
host->name = (char *)dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
return 0;
}
static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" },
{ }
};
U_BOOT_DRIVER(arasan_sdhci_drv) = {
.name = "arasan_sdhci",
.id = UCLASS_MMC,
.of_match = arasan_sdhci_ids,
.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
.probe = arasan_sdhci_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
};