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imx: mx7: default enable MDIO open drain 

The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2016-01-04 13:16:41 +08:00 committed by Stefano Babic
parent 9ba18ff8ef
commit d9699de85c
2 changed files with 22 additions and 0 deletions
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20
arch/arm/cpu/armv7/mx7/soc.c
View File

@ -130,6 +130,24 @@ static void init_csu(void)
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}
static void imx_enet_mdio_fixup(void)
{
struct iomuxc_gpr_base_regs *gpr_regs =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/*
* The management data input/output (MDIO) requires open-drain,
* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
* this feature. So to TO1.1, need to enable open drain by setting
* bits GPR0[8:7].
*/
if (soc_rev() >= CHIP_REV_1_1) {
setbits_le32(&gpr_regs->gpr[0],
IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
}
}
int arch_cpu_init(void)
{
init_aips();
@ -138,6 +156,8 @@ int arch_cpu_init(void)
/* Disable PDE bit of WMCR register */
imx_set_wdog_powerdown(false);
imx_enet_mdio_fixup();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();

2
arch/arm/include/asm/arch-mx7/imx-regs.h
View File

@ -272,6 +272,8 @@ struct src {
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
/* GPR1 Bit Fields */
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0