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mtd: OneNAND: add timeout to wait ready loops 

Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
This commit is contained in:
Ladislav Michl 2016-07-12 20:28:19 +02:00 committed by Tom Rini
parent 9a9d394639
commit d9098ee55f
1 changed files with 19 additions and 11 deletions
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30
drivers/mtd/onenand/onenand_base.c
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@ -20,6 +20,7 @@
*/ */
#include <common.h> #include <common.h>
#include <watchdog.h>
#include <linux/compat.h> #include <linux/compat.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#include "linux/mtd/flashchip.h" #include "linux/mtd/flashchip.h"
@ -467,15 +468,18 @@ static int onenand_read_ecc(struct onenand_chip *this)
static int onenand_wait(struct mtd_info *mtd, int state) static int onenand_wait(struct mtd_info *mtd, int state)
{ {
struct onenand_chip *this = mtd->priv; struct onenand_chip *this = mtd->priv;
unsigned int flags = ONENAND_INT_MASTER;
unsigned int interrupt = 0; unsigned int interrupt = 0;
unsigned int ctrl; unsigned int ctrl;
while (1) { /* Wait at most 20ms ... */
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
WATCHDOG_RESET();
if (get_timer(time_start) > timeo)
return -EIO;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
if (interrupt & flags) } while ((interrupt & ONENAND_INT_MASTER) == 0);
break;
}
ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
@ -1154,15 +1158,18 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from,
static int onenand_bbt_wait(struct mtd_info *mtd, int state) static int onenand_bbt_wait(struct mtd_info *mtd, int state)
{ {
struct onenand_chip *this = mtd->priv; struct onenand_chip *this = mtd->priv;
unsigned int flags = ONENAND_INT_MASTER;
unsigned int interrupt; unsigned int interrupt;
unsigned int ctrl; unsigned int ctrl;
while (1) { /* Wait at most 20ms ... */
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
WATCHDOG_RESET();
if (get_timer(time_start) > timeo)
return ONENAND_BBT_READ_FATAL_ERROR;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
if (interrupt & flags) } while ((interrupt & ONENAND_INT_MASTER) == 0);
break;
}
/* To get correct interrupt status in timeout case */ /* To get correct interrupt status in timeout case */
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
@ -2536,7 +2543,8 @@ static int onenand_chip_probe(struct mtd_info *mtd)
this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
/* Wait reset */ /* Wait reset */
this->wait(mtd, FL_RESETING); if (this->wait(mtd, FL_RESETING))
return -ENXIO;
/* Restore system configuration 1 */ /* Restore system configuration 1 */
this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);