ppc4xx: CPU PPC440x5 on Virtex5 FX
-This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Ricardo Ribalda Delgado
Stefan Roese
parent
42246dacf6
commit
d865fd0980
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@ -35,10 +35,8 @@ SOBJS += kgdb.o
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COBJS := 40x_spd_sdram.o
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COBJS += 44x_spd_ddr.o
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COBJS += 44x_spd_ddr2.o
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COBJS += 4xx_enet.o
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COBJS += 4xx_pci.o
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COBJS += 4xx_pcie.o
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COBJS += 4xx_uart.o
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COBJS += bedbug_405.o
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COBJS += commproc.o
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COBJS += cpu.o
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@ -47,11 +45,9 @@ COBJS += denali_data_eye.o
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COBJS += denali_spd_ddr2.o
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COBJS += ecc.o
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COBJS += fdt.o
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COBJS += gpio.o
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COBJS += i2c.o
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COBJS += interrupts.o
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COBJS += iop480_uart.o
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COBJS += miiphy.o
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COBJS += ndfc.o
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COBJS += sdram.o
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COBJS += speed.o
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@ -60,6 +56,15 @@ COBJS += traps.o
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COBJS += usb.o
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COBJS += usb_ohci.o
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COBJS += usbdev.o
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ifndef CONFIG_XILINX_440
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COBJS += 4xx_enet.o
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COBJS += 4xx_uart.o
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COBJS += gpio.o
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COBJS += miiphy.o
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COBJS += uic.o
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else
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COBJS += xilinx_irq.o
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endif
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -279,7 +279,11 @@ int checkcpu (void)
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get_sys_info(&sys_info);
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#if defined(CONFIG_XILINX_440)
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puts("IBM PowerPC 4");
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#else
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puts("AMCC PowerPC 4");
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#endif
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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@ -542,6 +546,10 @@ int checkcpu (void)
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strcpy(addstr, "No Security support");
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break;
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case PVR_VIRTEX5:
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puts("x5 VIRTEX5");
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break;
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default:
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printf (" UNKNOWN (PVR=%08x)", pvr);
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break;
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@ -8,6 +8,10 @@
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* (C) Copyright 2003 (440GX port)
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
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* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* Work supported by Qtechnology (htpp://qtec.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -31,23 +35,11 @@
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/interrupt.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#if (UIC_MAX > 3)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
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UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
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#elif (UIC_MAX > 2)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
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#elif (UIC_MAX > 1)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
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#else
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#define UICB0_ALL 0
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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@ -58,11 +50,7 @@ struct irq_action {
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void *arg;
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int count;
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};
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static struct irq_action irq_vecs[UIC_MAX * 32];
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u32 get_dcr(u16);
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void set_dcr(u16, u32);
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static struct irq_action irq_vecs[IRQ_MAX];
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#if defined(CONFIG_440)
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@ -103,7 +91,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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/*
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* Mark all irqs as free
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*/
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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for (vec = 0; vec < IRQ_MAX; vec++) {
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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irq_vecs[vec].count = 0;
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@ -147,110 +135,36 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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*/
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set_evpr(0x00000000);
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
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#endif
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/*
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*Call uic or xilinx_irq pic_enable
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*/
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pic_enable();
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return (0);
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}
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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void timer_interrupt_cpu(struct pt_regs *regs)
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{
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u32 uic_msr;
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u32 msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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set_dcr(uic_base + UIC_ER,
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get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec));
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printf("Masking bogus interrupt vector %d"
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" (UIC_BASE=0x%x)\n", vec, uic_base);
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}
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/*
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* After servicing the interrupt, we have to remove the
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* status indicator
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*/
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set_dcr(uic_base + UIC_SR, UIC_MASK(vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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u32 uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uic0msr);
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#if (UIC_MAX > 1)
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if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
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uic_interrupt(UIC1_DCR_BASE, 32);
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#endif
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#if (UIC_MAX > 2)
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if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
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uic_interrupt(UIC2_DCR_BASE, 64);
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#endif
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#if (UIC_MAX > 3)
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if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
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uic_interrupt(UIC3_DCR_BASE, 96);
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#endif
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if (uic_msr & ~(UICB0_ALL))
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uic_interrupt(UIC0_DCR_BASE, 0);
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mtdcr(uic0sr, uic_msr);
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/* nothing to do here */
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return;
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}
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void interrupt_run_handler(int vec)
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{
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler) (irq_vecs[vec].arg);
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} else {
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pic_irq_disable(vec);
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printf("Masking bogus interrupt vector %d\n", vec);
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}
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pic_irq_ack(vec);
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return;
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}
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/*
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* Install and free a interrupt handler.
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*/
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void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
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{
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/*
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@ -263,51 +177,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
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irq_vecs[vec].handler = handler;
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irq_vecs[vec].arg = arg;
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
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#endif
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debug("Install interrupt for vector %d ==> %p\n", vec, handler);
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pic_irq_enable(vec);
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return;
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}
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void irq_free_handler (int vec)
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void irq_free_handler(int vec)
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{
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debug("Free interrupt for vector %d ==> %p\n",
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vec, irq_vecs[vec].handler);
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
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#endif
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pic_irq_disable(vec);
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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}
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void timer_interrupt_cpu (struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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}
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@ -319,7 +201,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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printf ("Interrupt-Information:\n");
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printf ("Nr Routine Arg Count\n");
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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for (vec = 0; vec < IRQ_MAX; vec++) {
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if (irq_vecs[vec].handler != NULL) {
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printf ("%02d %08lx %08lx %d\n",
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vec,
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@ -416,7 +416,8 @@ ulong get_PCI_freq (void)
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return sys_info.freqPCI;
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}
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#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
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#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
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&& !defined(CONFIG_XILINX_440)
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void get_sys_info (sys_info_t * sysInfo)
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{
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unsigned long strp0;
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@ -449,6 +450,8 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqUART = sysInfo->freqPLB;
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}
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#else
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#if !defined(CONFIG_XILINX_440)
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void get_sys_info (sys_info_t * sysInfo)
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{
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unsigned long strp0;
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@ -535,6 +538,7 @@ void get_sys_info (sys_info_t * sysInfo)
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}
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#endif
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#endif /* CONFIG_XILINX_440 */
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#if defined(CONFIG_YUCCA)
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unsigned long determine_sysper(void)
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@ -0,0 +1,209 @@
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* (C) Copyright 2003 (440GX port)
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
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* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* Work supported by Qtechnology (htpp://qtec.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/interrupt.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#if (UIC_MAX > 3)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
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UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
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#elif (UIC_MAX > 2)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
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#elif (UIC_MAX > 1)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
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#else
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#define UICB0_ALL 0
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#endif
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u32 get_dcr(u16);
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DECLARE_GLOBAL_DATA_PTR;
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void pic_enable(void)
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{
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt,
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0);
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irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt,
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0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt,
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0);
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irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt,
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0);
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#endif
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt,
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0);
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irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt,
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0);
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#endif
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}
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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{
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u32 uic_msr;
|
||||
u32 msr_shift;
|
||||
int vec;
|
||||
|
||||
/*
|
||||
* Read masked interrupt status register to determine interrupt source
|
||||
*/
|
||||
uic_msr = get_dcr(uic_base + UIC_MSR);
|
||||
msr_shift = uic_msr;
|
||||
vec = vec_base;
|
||||
|
||||
while (msr_shift != 0) {
|
||||
if (msr_shift & 0x80000000)
|
||||
interrupt_run_handler(vec);
|
||||
/*
|
||||
* Shift msr to next position and increment vector
|
||||
*/
|
||||
msr_shift <<= 1;
|
||||
vec++;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle external interrupts
|
||||
*/
|
||||
void external_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
u32 uic_msr;
|
||||
|
||||
/*
|
||||
* Read masked interrupt status register to determine interrupt source
|
||||
*/
|
||||
uic_msr = mfdcr(uic0msr);
|
||||
|
||||
#if (UIC_MAX > 1)
|
||||
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
|
||||
(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
|
||||
uic_interrupt(UIC1_DCR_BASE, 32);
|
||||
#endif
|
||||
|
||||
#if (UIC_MAX > 2)
|
||||
if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
|
||||
(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
|
||||
uic_interrupt(UIC2_DCR_BASE, 64);
|
||||
#endif
|
||||
|
||||
#if (UIC_MAX > 3)
|
||||
if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
|
||||
(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
|
||||
uic_interrupt(UIC3_DCR_BASE, 96);
|
||||
#endif
|
||||
|
||||
if (uic_msr & ~(UICB0_ALL))
|
||||
uic_interrupt(UIC0_DCR_BASE, 0);
|
||||
|
||||
mtdcr(uic0sr, uic_msr);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void pic_irq_ack(unsigned int vec)
|
||||
{
|
||||
|
||||
if ((vec >= 0) && (vec < 32))
|
||||
mtdcr(uicsr, UIC_MASK(vec));
|
||||
#if (UIC_MAX > 1)
|
||||
else if ((vec >= 32) && (vec < 64))
|
||||
mtdcr(uic1sr, UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 2)
|
||||
else if ((vec >= 64) && (vec < 96))
|
||||
mtdcr(uic2sr, UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 3)
|
||||
else if (vec >= 96)
|
||||
mtdcr(uic3sr, UIC_MASK(vec));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Install and free a interrupt handler.
|
||||
*/
|
||||
void pic_irq_enable(unsigned int vec)
|
||||
{
|
||||
|
||||
if ((vec >= 0) && (vec < 32))
|
||||
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
|
||||
#if (UIC_MAX > 1)
|
||||
else if ((vec >= 32) && (vec < 64))
|
||||
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 2)
|
||||
else if ((vec >= 64) && (vec < 96))
|
||||
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 3)
|
||||
else if (vec >= 96)
|
||||
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
|
||||
#endif
|
||||
|
||||
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
|
||||
}
|
||||
|
||||
void pic_irq_disable(unsigned int vec)
|
||||
{
|
||||
|
||||
if ((vec >= 0) && (vec < 32))
|
||||
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
|
||||
#if (UIC_MAX > 1)
|
||||
else if ((vec >= 32) && (vec < 64))
|
||||
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 2)
|
||||
else if ((vec >= 64) && (vec < 96))
|
||||
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
|
||||
#endif
|
||||
#if (UIC_MAX > 3)
|
||||
else if (vec >= 96)
|
||||
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
|
||||
* This work has been supported by: QTechnology http://qtec.com/
|
||||
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <commproc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/xilinx_irq.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void pic_enable(void)
|
||||
{
|
||||
debug("Xilinx PIC at 0x%8x\n", intc);
|
||||
|
||||
/*
|
||||
* Disable all external interrupts until they are
|
||||
* explicitly requested.
|
||||
*/
|
||||
out_be32((u32 *) IER, 0);
|
||||
|
||||
/* Acknowledge any pending interrupts just in case. */
|
||||
out_be32((u32 *) IAR, 0xffffffff);
|
||||
|
||||
/* Turn on the Master Enable. */
|
||||
out_be32((u32 *) MER, 0x3UL);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int xilinx_pic_irq_get(void)
|
||||
{
|
||||
u32 irq;
|
||||
irq = in_be32((u32 *) IVR);
|
||||
|
||||
/* If no interrupt is pending then all bits of the IVR are set to 1. As
|
||||
* the IVR is as many bits wide as numbers of inputs are available.
|
||||
* Therefore, if all bits of the IVR are set to one, its content will
|
||||
* be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS.
|
||||
*/
|
||||
if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS)
|
||||
irq = -1; /* report no pending interrupt. */
|
||||
|
||||
debug("get_irq: %d\n", irq);
|
||||
return (irq);
|
||||
}
|
||||
|
||||
void pic_irq_enable(unsigned int irq)
|
||||
{
|
||||
u32 mask = IRQ_MASK(irq);
|
||||
debug("enable: %d\n", irq);
|
||||
out_be32((u32 *) SIE, mask);
|
||||
}
|
||||
|
||||
void pic_irq_disable(unsigned int irq)
|
||||
{
|
||||
u32 mask = IRQ_MASK(irq);
|
||||
debug("disable: %d\n", irq);
|
||||
out_be32((u32 *) CIE, mask);
|
||||
}
|
||||
|
||||
void pic_irq_ack(unsigned int irq)
|
||||
{
|
||||
u32 mask = IRQ_MASK(irq);
|
||||
debug("ack: %d\n", irq);
|
||||
out_be32((u32 *) IAR, mask);
|
||||
}
|
||||
|
||||
void external_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
int irq;
|
||||
|
||||
irq = xilinx_pic_irq_get();
|
||||
if (irq < 0)
|
||||
return;
|
||||
|
||||
interrupt_run_handler(irq);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
|
||||
* This work has been supported by: QTechnology http://qtec.com/
|
||||
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef INTERRUPT_H
|
||||
#define INTERRUPT_H
|
||||
|
||||
#if defined(CONFIG_XILINX_440)
|
||||
#include <asm/xilinx_irq.h>
|
||||
#else
|
||||
#include <asm/ppc4xx-uic.h>
|
||||
#endif
|
||||
|
||||
void pic_enable(void);
|
||||
void pic_irq_enable(unsigned int irq);
|
||||
void pic_irq_disable(unsigned int irq);
|
||||
void pic_irq_ack(unsigned int irq);
|
||||
void external_interrupt(struct pt_regs *regs);
|
||||
void interrupt_run_handler(int vec);
|
||||
|
||||
#endif
|
||||
|
|
@ -43,6 +43,8 @@
|
|||
#define UIC_MAX 1
|
||||
#endif
|
||||
|
||||
#define IRQ_MAX UIC_MAX * 32
|
||||
|
||||
/*
|
||||
* UIC register
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -859,6 +859,8 @@
|
|||
#define PVR_86xx 0x80040000
|
||||
#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
|
||||
|
||||
#define PVR_VIRTEX5 0x7ff21912
|
||||
|
||||
/*
|
||||
* For the 8xx processors, all of them report the same PVR family for
|
||||
* the PowerPC core. The various versions of these processors must be
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
|
||||
* This work has been supported by: QTechnology http://qtec.com/
|
||||
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef XILINX_IRQ_H
|
||||
#define XILINX_IRQ_H
|
||||
|
||||
#define intc XPAR_INTC_0_BASEADDR
|
||||
#define ISR (intc+(0*4)) /* Interrupt Status Register */
|
||||
#define IPR (intc+(1*4)) /* Interrupt Pending Register */
|
||||
#define IER (intc+(2*4)) /* Interrupt Enable Register */
|
||||
#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
|
||||
#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
|
||||
#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
|
||||
#define IVR (intc+(6*4)) /* Interrupt Vector Register */
|
||||
#define MER (intc+(7*4)) /* Master Enable Register */
|
||||
|
||||
#define IRQ_MASK(irq) (1<<(irq&0x1f))
|
||||
|
||||
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
#endif
|
||||
|
|
@ -54,7 +54,9 @@
|
|||
|
||||
#include <asm/ppc4xx-sdram.h>
|
||||
#include <asm/ppc4xx-ebc.h>
|
||||
#if !defined(CONFIG_XILINX_440)
|
||||
#include <asm/ppc4xx-uic.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro for generating register field mnemonics
|
||||
|
|
|
|||
Loading…
Reference in New Issue