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powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff 

When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2013-06-25 11:37:45 -07:00
parent 1cb19fbb31
commit d8556db1d4
2 changed files with 9 additions and 3 deletions
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4
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1585,8 +1585,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
} else {
debug("FSLDDR: setting bnds to 0 for inactive CS\n");
ddr->cs[i].bnds = 0;
/* setting bnds to 0xffffffff for inactive CS */
ddr->cs[i].bnds = 0xffffffff;
}
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);

8
arch/powerpc/cpu/mpc8xxx/ddr/main.c
View File

@ -504,7 +504,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
if (reg->cs[j].config & 0x80000000) {
unsigned int end;
end = reg->cs[j].bnds & 0xFFF;
/*
* 0xfffffff is a special value we put
* for unused bnds
*/
if (reg->cs[j].bnds == 0xffffffff)
continue;
end = reg->cs[j].bnds & 0xffff;
if (end > max_end) {
max_end = end;
}