V3s_Allwinner
/
uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 2 Wiki Activity

tegra: fdt: remove clocks nodes 

These nodes are unused.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Allen Martin 2013-01-16 13:11:21 +00:00 committed by Tom Warren
parent d08b9e9c7e
commit d3f8752ed6
12 changed files with 0 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/dts/tegra20.dtsi
View File

@ -10,16 +10,6 @@
#clock-cells = <1>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
intc: interrupt-controller@50041000 {
compatible = "nvidia,tegra20-gic";
interrupt-controller;

10
arch/arm/dts/tegra30.dtsi
View File

@ -9,16 +9,6 @@
#clock-cells = <1>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
i2c@7000c000 {
#address-cells = <1>;
#size-cells = <0>;

14
board/avionic-design/dts/tegra20-medcom-wide.dts
View File

@ -14,16 +14,6 @@
reg = <0x00000000 0x20000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
host1x {
status = "okay";
@ -37,10 +27,6 @@
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = <216000000>;
};

14
board/avionic-design/dts/tegra20-plutux.dts
View File

@ -14,20 +14,6 @@
reg = <0x00000000 0x20000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = <216000000>;
};

14
board/avionic-design/dts/tegra20-tec.dts
View File

@ -14,16 +14,6 @@
reg = <0x00000000 0x20000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
host1x {
status = "okay";
@ -37,10 +27,6 @@
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = <216000000>;
};

13
board/compal/dts/tegra20-paz00.dts
View File

@ -14,19 +14,6 @@
reg = <0x00000000 0x20000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006000 {
clock-frequency = < 216000000 >;
};

13
board/compulab/dts/tegra20-trimslice.dts
View File

@ -15,19 +15,6 @@
reg = <0x00000000 0x40000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006000 {
clock-frequency = <216000000>;
};

13
board/nvidia/dts/tegra20-harmony.dts
View File

@ -15,19 +15,6 @@
reg = <0x00000000 0x40000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = < 216000000 >;
};

10
board/nvidia/dts/tegra20-seaboard.dts
View File

@ -45,16 +45,6 @@
};
};
clocks {
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = < 216000000 >;
};

13
board/nvidia/dts/tegra20-ventana.dts
View File

@ -14,19 +14,6 @@
reg = <0x00000000 0x40000000>;
};
clocks {
clk_32k: clk_32k {
clock-frequency = <32000>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006300 {
clock-frequency = < 216000000 >;
};

10
board/nvidia/dts/tegra20-whistler.dts
View File

@ -16,16 +16,6 @@
reg = < 0x00000000 0x20000000 >;
};
clocks {
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
serial@70006000 {
clock-frequency = < 216000000 >;
};

13
board/nvidia/dts/tegra30-cardhu.dts
View File

@ -20,19 +20,6 @@
reg = <0x80000000 0x40000000>;
};
clocks {
clk_32k: clk_32K {
clock-frequency = <32768>;
};
osc {
clock-frequency = <12000000>;
};
};
clock@60006000 {
clocks = <&clk_32k &osc>;
};
i2c@7000c000 {
clock-frequency = <100000>;
};