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ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766 

RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Nishanth Menon 2015-03-09 17:12:09 -05:00 committed by Tom Rini
parent c6f90e1418
commit cdef0b3f3a
4 changed files with 37 additions and 32 deletions
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45
arch/arm/cpu/armv7/omap3/board.c
View File

@ -415,30 +415,29 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
void __weak omap3_set_aux_cr_secure(u32 acr)
{
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
emu_romcode_params.param1 = acr;
omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
(u32 *)&emu_romcode_params);
}
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
if (get_device_type() == GP_DEVICE) {
/* Write ACR - affects secure banked bits */
if (get_device_type() == GP_DEVICE)
omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
} else {
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
emu_romcode_params.param1 = acr;
omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
(u32 *)&emu_romcode_params);
}
else
omap3_set_aux_cr_secure(acr);
/* Write ACR - affects non-secure banked bits - some erratas need it */
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
}
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
@ -449,9 +448,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
/* Write ACR - affects non-secure banked bits */
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
/* Invalidate the entire L2 cache from secure mode */
@ -470,10 +468,9 @@ static void omap3_invalidate_l2_cache_secure(void)
void v7_outer_cache_enable(void)
{
/* Set L2EN */
omap3_update_aux_cr_secure(0x2, 0);
/*
* Set L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in setting both banked bits(in fact this is required
* by an erratum)
@ -483,10 +480,8 @@ void v7_outer_cache_enable(void)
void omap3_outer_cache_disable(void)
{
/* Clear L2EN */
omap3_update_aux_cr_secure(0, 0x2);
/*
* Clear L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in clearing both banked bits(in fact this is required
* by an erratum)

1
arch/arm/include/asm/arch-omap3/sys_proto.h
View File

@ -73,5 +73,6 @@ void power_init_r(void);
void dieid_num_r(void);
void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
#endif

19
board/nokia/rx51/rx51.c
View File

@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
void omap3_set_aux_cr_secure(u32 acr)
{
struct emu_hal_params_rx51 emu_romcode_params = { 0, };
emu_romcode_params.num_params = 2;
emu_romcode_params.param1 = acr;
omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
(u32 *)&emu_romcode_params);
}
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
@ -350,19 +361,13 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
emu_romcode_params.num_params = 2;
emu_romcode_params.param1 = acr;
omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
(u32 *)&emu_romcode_params);
omap3_set_aux_cr_secure(acr);
}
/*

4
include/configs/nokia_rx51.h
View File

@ -29,6 +29,10 @@
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51