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microblaze: Fix irq.S code 

It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek 2010-04-16 11:30:16 +02:00
parent 398b1d57a6
commit cc53690e05
1 changed files with 62 additions and 120 deletions
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182
arch/microblaze/cpu/irq.S
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@ -27,129 +27,71 @@
.text .text
.global _interrupt_handler .global _interrupt_handler
_interrupt_handler: _interrupt_handler:
addi r1, r1, -4 swi r2, r1, -4
swi r2, r1, 0 swi r3, r1, -8
addi r1, r1, -4 swi r4, r1, -12
swi r3, r1, 0 swi r5, r1, -16
addi r1, r1, -4 swi r6, r1, -20
swi r4, r1, 0 swi r7, r1, -24
addi r1, r1, -4 swi r8, r1, -28
swi r5, r1, 0 swi r9, r1, -32
addi r1, r1, -4 swi r10, r1, -36
swi r6, r1, 0 swi r11, r1, -40
addi r1, r1, -4 swi r12, r1, -44
swi r7, r1, 0 swi r13, r1, -48
addi r1, r1, -4 swi r14, r1, -52
swi r8, r1, 0 swi r15, r1, -56
addi r1, r1, -4 swi r16, r1, -60
swi r9, r1, 0 swi r17, r1, -64
addi r1, r1, -4 swi r18, r1, -68
swi r10, r1, 0 swi r19, r1, -72
addi r1, r1, -4 swi r20, r1, -76
swi r11, r1, 0 swi r21, r1, -80
addi r1, r1, -4 swi r22, r1, -84
swi r12, r1, 0 swi r23, r1, -88
addi r1, r1, -4 swi r24, r1, -92
swi r13, r1, 0 swi r25, r1, -96
addi r1, r1, -4 swi r26, r1, -100
swi r14, r1, 0 swi r27, r1, -104
addi r1, r1, -4 swi r28, r1, -108
swi r15, r1, 0 swi r29, r1, -112
addi r1, r1, -4 swi r30, r1, -116
swi r16, r1, 0 swi r31, r1, -120
addi r1, r1, -4 addik r1, r1, -124
swi r17, r1, 0
addi r1, r1, -4
swi r18, r1, 0
addi r1, r1, -4
swi r19, r1, 0
addi r1, r1, -4
swi r20, r1, 0
addi r1, r1, -4
swi r21, r1, 0
addi r1, r1, -4
swi r22, r1, 0
addi r1, r1, -4
swi r23, r1, 0
addi r1, r1, -4
swi r24, r1, 0
addi r1, r1, -4
swi r25, r1, 0
addi r1, r1, -4
swi r26, r1, 0
addi r1, r1, -4
swi r27, r1, 0
addi r1, r1, -4
swi r28, r1, 0
addi r1, r1, -4
swi r29, r1, 0
addi r1, r1, -4
swi r30, r1, 0
addi r1, r1, -4
swi r31, r1, 0
brlid r15, interrupt_handler brlid r15, interrupt_handler
nop nop
nop nop
lwi r31, r1, 0 addik r1, r1, 124
addi r1, r1, 4 lwi r31, r1, -120
lwi r30, r1, 0 lwi r30, r1, -116
addi r1, r1, 4 lwi r29, r1, -112
lwi r29, r1, 0 lwi r28, r1, -108
addi r1, r1, 4 lwi r27, r1, -104
lwi r28, r1, 0 lwi r26, r1, -100
addi r1, r1, 4 lwi r25, r1, -96
lwi r27, r1, 0 lwi r24, r1, -92
addi r1, r1, 4 lwi r23, r1, -88
lwi r26, r1, 0 lwi r22, r1, -84
addi r1, r1, 4 lwi r21, r1, -80
lwi r25, r1, 0 lwi r20, r1, -76
addi r1, r1, 4 lwi r19, r1, -72
lwi r24, r1, 0 lwi r18, r1, -68
addi r1, r1, 4 lwi r17, r1, -64
lwi r23, r1, 0 lwi r16, r1, -60
addi r1, r1, 4 lwi r15, r1, -56
lwi r22, r1, 0 lwi r14, r1, -52
addi r1, r1, 4 lwi r13, r1, -48
lwi r21, r1, 0 lwi r12, r1, -44
addi r1, r1, 4 lwi r11, r1, -40
lwi r20, r1, 0 lwi r10, r1, -36
addi r1, r1, 4 lwi r9, r1, -32
lwi r19, r1, 0 lwi r8, r1, -28
addi r1, r1, 4 lwi r7, r1, -24
lwi r18, r1, 0 lwi r6, r1, -20
addi r1, r1, 4 lwi r5, r1, -16
lwi r17, r1, 0 lwi r4, r1, -12
addi r1, r1, 4 lwi r3, r1, -8
lwi r16, r1, 0 lwi r2, r1, -4
addi r1, r1, 4
lwi r15, r1, 0
addi r1, r1, 4
lwi r14, r1, 0
addi r1, r1, 4
lwi r13, r1, 0
addi r1, r1, 4
lwi r12, r1, 0
addi r1, r1, 4
lwi r11, r1, 0
addi r1, r1, 4
lwi r10, r1, 0
addi r1, r1, 4
lwi r9, r1, 0
addi r1, r1, 4
lwi r8, r1, 0
addi r1, r1, 4
lwi r7, r1, 0
addi r1, r1, 4
lwi r6, r1, 0
addi r1, r1, 4
lwi r5, r1, 0
addi r1, r1, 4
lwi r4, r1, 0
addi r1, r1, 4
lwi r3, r1, 0
addi r1, r1, 4
lwi r2, r1, 0
addi r1, r1, 4
/* enable_interrupt */ /* enable_interrupt */
#ifdef XILINX_USE_MSR_INSTR #ifdef XILINX_USE_MSR_INSTR