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White space cleanup. 

Some 80-column cleanups.
Convert printf() to puts() where possible.
Use #include "spd_sdram.h" as needed.
Enhanced reset command usage message a bit.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger 2006-05-31 12:44:44 -05:00
parent 3d5c5be547
commit cb5965fb95
2 changed files with 127 additions and 121 deletions
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79
board/mpc8641hpcn/mpc8641hpcn.c
View File

@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd);
#include "pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
extern long int spd_sdram(void);
#if defined(CONFIG_SPD_EEPROM)
#include "spd_sdram.h"
#endif
void sdram_init(void);
long int fixed_sdram(void);
@ -69,25 +70,23 @@ int checkboard (void)
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
if ((io_sel==2 || io_sel==3 || io_sel==5 \
|| io_sel==6 || io_sel==7 || io_sel==0xF)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
debug ("PCI-EXPRESS 1: %s \n",
pex1_agent ? "Agent" : "Host");
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
if ((io_sel == 2 || io_sel == 3 || io_sel == 5
|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
if (pex1->pme_msg_det) {
pex1->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",
debug(" with errors. Clearing. Now 0x%08x",
pex1->pme_msg_det);
}
debug ("\n");
} else {
printf ("PCI-EXPRESS 1: Disabled\n");
puts("PCI-EXPRESS 1: Disabled\n");
}
#else
printf("PCI-EXPRESS1: Disabled\n");
puts("PCI-EXPRESS1: Disabled\n");
#endif
return 0;
@ -98,7 +97,6 @@ long int
initdram(int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
@ -130,7 +128,7 @@ int testdram(void)
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
puts("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
@ -141,7 +139,7 @@ int testdram(void)
}
}
printf("SDRAM test phase 2:\n");
puts("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
@ -152,7 +150,7 @@ int testdram(void)
}
}
printf("SDRAM test passed.\n");
puts("SDRAM test passed.\n");
return 0;
}
#endif
@ -257,7 +255,6 @@ ft_board_setup(void *blob, bd_t *bd)
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
}
#endif
@ -269,7 +266,14 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong val;
ulong corepll;
if (argc > 1) {
/*
* No args is a simple reset request.
*/
if (argv <= 0) {
out8(PIXIS_BASE + PIXIS_RST, 0);
/* not reached */
}
cmd = argv[1][1];
switch (cmd) {
case 'f': /* reset with frequency changed */
@ -283,9 +287,9 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
printf("Setting registers VCFGEN0 and VCTL\n");
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
@ -303,11 +307,11 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
if (val == 3) {
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else
goto my_usage;
@ -315,26 +319,32 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
while(1); /* Not reached */
} else if(argv[2][1] == 'd'){
/* Reset from next bank without changing frequencies but with watchdog timer enabled */
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while(1); /* Not reached */
} else {
/* Reset from next bank without changing frequency and without watchdog timer enabled */
/*
* Reset from next bank without changing
* frequency and without watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Resetting board to boot from the other bank....\n");
puts("Resetting board to boot from the other bank....\n");
set_px_go();
}
@ -343,12 +353,9 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
my_usage:
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
printf("For example: reset cf 40 2.5 10\n");
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
return;
} else
out8(PIXIS_BASE+PIXIS_RST,0);
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
puts(" reset altbank [wd]\n");
puts("For example: reset cf 40 2.5 10\n");
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
}

27
cpu/mpc86xx/cpu.c
View File

@ -1,6 +1,6 @@
/*
* Copyright 2004 Freescale Semiconductor
* Jeff Brown (jeffrey@freescale.com)
* Copyright 2006 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -55,8 +55,7 @@ int checkcpu (void)
minor = PVR_MIN(pvr);
puts("CPU:\n");
printf(" Core: ");
puts(" Core: ");
switch (ver) {
case PVR_VER(PVR_86xx):
@ -112,11 +111,11 @@ int checkcpu (void)
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
printf(" L2: ");
puts(" L2: ");
if (get_l2cr() & 0x80000000)
printf("Enabled\n");
puts("Enabled\n");
else
printf("Disabled\n");
puts("Disabled\n");
return 0;
}
@ -125,7 +124,6 @@ int checkcpu (void)
static inline void
soft_restart(unsigned long addr)
{
#ifndef CONFIG_MPC8641HPCN
/* SRR0 has system reset vector, SRR1 has default MSR value */
@ -137,8 +135,11 @@ soft_restart(unsigned long addr)
__asm__ __volatile__ ("rfi");
#else /* CONFIG_MPC8641HPCN */
out8(PIXIS_BASE+PIXIS_RST,0);
out8(PIXIS_BASE + PIXIS_RST, 0);
#endif /* !CONFIG_MPC8641HPCN */
while(1); /* not reached */
}
@ -149,10 +150,10 @@ soft_restart(unsigned long addr)
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
#ifndef CONFIG_MPC8641HPCN
#ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS;
ulong addr = CFG_RESET_ADDRESS;
#else
/*
* note: when CFG_MONITOR_BASE points to a RAM address,
@ -160,11 +161,9 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* address. Better pick an address known to be invalid on your
* system and assign it to CFG_RESET_ADDRESS.
*/
addr = CFG_MONITOR_BASE - sizeof (ulong);
ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
#endif
#ifndef CONFIG_MPC8641HPCN
/* flush and disable I/D cache */
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");