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mpc83xx: MPC837XEMDS: Fixup eSDHC nodes in device tree 

fdt_fixup_esdhc() will either disable or enable eSDHC nodes, and
also will fixup clock-frequency property.

Plus, since DR USB and eSDHC are mutually exclusive, we should
only configure the eSDHC if asked through hwconfig.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Anton Vorontsov 2009-06-10 00:25:31 +04:00 committed by Wolfgang Denk
parent c9646ed758
commit c78c678354
2 changed files with 25 additions and 13 deletions
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37
board/freescale/mpc837xemds/mpc837xemds.c
View File

@ -11,6 +11,7 @@
*/ */
#include <common.h> #include <common.h>
#include <hwconfig.h>
#include <i2c.h> #include <i2c.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
@ -18,12 +19,12 @@
#include <tsec.h> #include <tsec.h>
#include <libfdt.h> #include <libfdt.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <fsl_esdhc.h>
#include "pci.h" #include "pci.h"
#include "../common/pq-mds-pib.h" #include "../common/pq-mds-pib.h"
int board_early_init_f(void) int board_early_init_f(void)
{ {
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */ /* Enable flash write */
@ -31,18 +32,6 @@ int board_early_init_f(void)
/* Clear all of the interrupt of BCSR */ /* Clear all of the interrupt of BCSR */
bcsr[0xe] = 0xff; bcsr[0xe] = 0xff;
#ifdef CONFIG_MMC
/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
bcsr[0xc] |= 0x4c;
/* Set proper bits in SICR to allow SD signals through */
clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI),
(SICRH_GPIO2_E_SD | SICRH_SPI_SD));
#endif
#ifdef CONFIG_FSL_SERDES #ifdef CONFIG_FSL_SERDES
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr = in_be32(&immr->sysconf.spridr); u32 spridr = in_be32(&immr->sysconf.spridr);
@ -72,6 +61,27 @@ int board_early_init_f(void)
return 0; return 0;
} }
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
if (!hwconfig("esdhc"))
return 0;
/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
bcsr[0xc] |= 0x4c;
/* Set proper bits in SICR to allow SD signals through */
clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
SICRH_GPIO2_E_SD | SICRH_SPI_SD);
return fsl_esdhc_mmc_init(bd);
}
#endif
#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
int board_eth_init(bd_t *bd) int board_eth_init(bd_t *bd)
{ {
@ -322,6 +332,7 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd); ft_cpu_setup(blob, bd);
ft_tsec_fixup(blob, bd); ft_tsec_fixup(blob, bd);
fdt_fixup_dr_usb(blob, bd); fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
ft_pci_setup(blob, bd); ft_pci_setup(blob, bd);
if (board_pci_host_broken()) if (board_pci_host_broken())

1
include/configs/MPC837XEMDS.h
View File

@ -111,6 +111,7 @@
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_HWCONFIG
/* /*
* IMMR new address * IMMR new address