Merge branch 'master' of git://git.denx.de/u-boot-sh
This commit is contained in:
Wolfgang Denk
commit
c6b734f5ae
|
|
@ -1011,6 +1011,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|||
SH7763RDP SH7763
|
||||
RSK7203 SH7203
|
||||
AP325RXA SH7723
|
||||
SHMIN SH7706
|
||||
|
||||
Mark Jonas <mark.jonas@de.bosch.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -31,7 +31,9 @@
|
|||
#define CACHE_OC_NUM_ENTRIES 256
|
||||
#define CACHE_OC_ENTRY_SHIFT 4
|
||||
|
||||
#if defined(CONFIG_CPU_SH7710)
|
||||
#if defined(CONFIG_CPU_SH7706)
|
||||
#include <asm/cpu_sh7706.h>
|
||||
#elif defined(CONFIG_CPU_SH7710)
|
||||
#include <asm/cpu_sh7710.h>
|
||||
#elif defined(CONFIG_CPU_SH7720)
|
||||
#include <asm/cpu_sh7720.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
#ifndef _ASM_CPU_SH7706_H_
|
||||
#define _ASM_CPU_SH7706_H_
|
||||
|
||||
#define CACHE_OC_NUM_WAYS 4
|
||||
#define CCR_CACHE_INIT 0x0000000D
|
||||
|
||||
/* MMU and Cache control */
|
||||
#define MMUCR 0xFFFFFFE0
|
||||
#define CCR 0xFFFFFFEC
|
||||
|
||||
/* PFC */
|
||||
#define PACR 0xA4050100
|
||||
#define PBCR 0xA4050102
|
||||
#define PCCR 0xA4050104
|
||||
#define PETCR 0xA4050106
|
||||
|
||||
/* Port Data Registers */
|
||||
#define PADR 0xA4050120
|
||||
#define PBDR 0xA4050122
|
||||
#define PCDR 0xA4050124
|
||||
|
||||
/* BSC */
|
||||
#define FRQCR 0xffffff80
|
||||
#define BCR1 0xffffff60
|
||||
#define BCR2 0xffffff62
|
||||
#define WCR1 0xffffff64
|
||||
#define WCR2 0xffffff66
|
||||
#define MCR 0xffffff68
|
||||
|
||||
/* SDRAM controller */
|
||||
#define DCR 0xffffff6a
|
||||
#define RTCSR 0xffffff6e
|
||||
#define RTCNT 0xffffff70
|
||||
#define RTCOR 0xffffff72
|
||||
#define RFCR 0xffffff74
|
||||
#define SDMR 0xFFFFD000
|
||||
#define CS3_R 0xFFFFE460
|
||||
|
||||
/* SCIF */
|
||||
#define SCSMR_2 0xA4000150
|
||||
#define SCIF0_BASE SCSMR_2
|
||||
|
||||
/* Timer */
|
||||
#define TSTR0 0xFFFFFE92
|
||||
#define TSTR TSTR0
|
||||
#define TCNT0 0xFFFFFE98
|
||||
#define TCR0 0xFFFFFE9C
|
||||
|
||||
/* On chip oscillator circuits */
|
||||
#define WTCNT 0xFFFFFF84
|
||||
#define WTCSR 0xFFFFFF86
|
||||
|
||||
#endif /* _ASM_CPU_SH7706_H_ */
|
||||
|
|
@ -325,44 +325,6 @@
|
|||
#define SPICR1 0xA4420030
|
||||
|
||||
/* SCIF */
|
||||
/*
|
||||
#define SCSMR 0xFFE00000
|
||||
#define SCBRR 0xFFE00004
|
||||
#define SCSCR 0xFFE00008
|
||||
#define SCFTDR 0xFFE0000C
|
||||
#define SCFSR 0xFFE00010
|
||||
#define SCFRDR 0xFFE00014
|
||||
#define SCFCR 0xFFE00018
|
||||
#define SCFDR 0xFFE0001C
|
||||
#define SCLSR 0xFFE00024
|
||||
#define SCSMR1 0xFFE10000
|
||||
#define SCBRR1 0xFFE10004
|
||||
#define SCSCR1 0xFFE10008
|
||||
#define SCFTDR1 0xFFE1000C
|
||||
#define SCFSR1 0xFFE10010
|
||||
#define SCFRDR1 0xFFE10014
|
||||
#define SCFCR1 0xFFE10018
|
||||
#define SCFDR1 0xFFE1001C
|
||||
#define SCLSR1 0xFFE10024
|
||||
#define SCSMR2 0xFFE20000
|
||||
#define SCBRR2 0xFFE20004
|
||||
#define SCSCR2 0xFFE20008
|
||||
#define SCFTDR2 0xFFE2000C
|
||||
#define SCFSR2 0xFFE20010
|
||||
#define SCFRDR2 0xFFE20014
|
||||
#define SCFCR2 0xFFE20018
|
||||
#define SCFDR2 0xFFE2001C
|
||||
#define SCLSR2 0xFFE20024
|
||||
#define SCSMR3 0xFFE30000
|
||||
#define SCBRR3 0xFFE30004
|
||||
#define SCSCR3 0xFFE30008
|
||||
#define SCFTDR3 0xFFE3000C
|
||||
#define SCFSR3 0xFFE30010
|
||||
#define SCFRDR3 0xFFE30014
|
||||
#define SCFCR3 0xFFE30018
|
||||
#define SCFDR3 0xFFE3001C
|
||||
#define SCLSR3 0xFFE30024
|
||||
*/
|
||||
#define SCIF0_BASE 0xFFE00000
|
||||
|
||||
/* SIM */
|
||||
|
|
|
|||
|
|
@ -166,26 +166,10 @@
|
|||
|
||||
/* SCI */
|
||||
#define SCSMR1 0xFFE00000
|
||||
#define SCBRR1 0xFFE00004
|
||||
#define SCSCR1 0xFFE00008
|
||||
#define SCTDR1 0xFFE0000C
|
||||
#define SCSSR1 0xFFE00010
|
||||
#define SCRDR1 0xFFE00014
|
||||
#define SCSCMR1 0xFFE00018
|
||||
#define SCSPTR1 0xFFE0001C
|
||||
#define SCF0_BASE SCSMR1
|
||||
|
||||
/* SCIF */
|
||||
#define SCSMR2 0xFFE80000
|
||||
#define SCBRR2 0xFFE80004
|
||||
#define SCSCR2 0xFFE80008
|
||||
#define SCFTDR2 0xFFE8000C
|
||||
#define SCFSR2 0xFFE80010
|
||||
#define SCFRDR2 0xFFE80014
|
||||
#define SCFCR2 0xFFE80018
|
||||
#define SCFDR2 0xFFE8001C
|
||||
#define SCSPTR2 0xFFE80020
|
||||
#define SCLSR2 0xFFE80024
|
||||
#define SCIF1_BASE SCSMR2
|
||||
|
||||
/* H-UDI */
|
||||
|
|
|
|||
|
|
@ -333,27 +333,8 @@
|
|||
#define RYRAR 0xFFE80054
|
||||
|
||||
/* Serial Communication Interface with FIFO */
|
||||
#define SCIF0_BASE SCSMR0
|
||||
#define SCSMR0 0xFFE00000
|
||||
#define SCBRR0 0xFFE00004
|
||||
#define SCSCR0 0xFFE00008
|
||||
#define SCFSR0 0xFFE00010
|
||||
#define SCFCR0 0xFFE00018
|
||||
#define SCTFDR0 0xFFE0001C
|
||||
#define SCRFDR0 0xFFE00020
|
||||
#define SCSPTR0 0xFFE00024
|
||||
#define SCLSR0 0xFFE00028
|
||||
#define SCRER0 0xFFE0002C
|
||||
#define SCSMR1 0xFFE10000
|
||||
#define SCBRR1 0xFFE10004
|
||||
#define SCSCR1 0xFFE10008
|
||||
#define SCFSR1 0xFFE10010
|
||||
#define SCFCR1 0xFFE10018
|
||||
#define SCTFDR1 0xFFE1001C
|
||||
#define SCRFDR1 0xFFE10020
|
||||
#define SCSPTR1 0xFFE10024
|
||||
#define SCLSR1 0xFFE10028
|
||||
#define SCRER1 0xFFE1002C
|
||||
#define SCIF0_BASE SCSMR0
|
||||
|
||||
/* Serial I/O with FIFO */
|
||||
#define SIMDR 0xFFE20000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Renesas Solutions Corp.
|
||||
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ZIMAGE_H_
|
||||
#define _ASM_ZIMAGE_H_
|
||||
|
||||
#define MOUNT_ROOT_RDONLY 0x000
|
||||
#define RAMDISK_FLAGS 0x004
|
||||
#define ORIG_ROOT_DEV 0x008
|
||||
#define LOADER_TYPE 0x00c
|
||||
#define INITRD_START 0x010
|
||||
#define INITRD_SIZE 0x014
|
||||
#define COMMAND_LINE 0x100
|
||||
|
||||
#define RD_PROMPT (1<<15)
|
||||
#define RD_DOLOAD (1<<14)
|
||||
#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
|
||||
#define CMD_ARG_RD_DOLOAD "load_ramdisk="
|
||||
|
||||
#endif
|
||||
|
|
@ -31,6 +31,9 @@ COBJS-y += time_sh2.o
|
|||
else
|
||||
COBJS-y += time.o
|
||||
endif
|
||||
ifeq ($(CONFIG_CMD_SH_ZIMAGEBOOT),y)
|
||||
COBJS-y += zimageboot.o
|
||||
endif
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2007,2008
|
||||
* Copyright (C) 2007, 2008, 2010
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -46,7 +46,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
|
|||
static int sh_flash_init(void)
|
||||
{
|
||||
gd->bd->bi_flashsize = flash_init();
|
||||
printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
|
||||
|
||||
if (gd->bd->bi_flashsize >= (1024 * 1024))
|
||||
printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
|
||||
else
|
||||
printf("FLASH: %ldKB\n", gd->bd->bi_flashsize / 1024);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/zimage.h>
|
||||
|
||||
#ifdef CONFIG_SYS_DEBUG
|
||||
static void hexdump(unsigned char *buf, int len)
|
||||
|
|
@ -43,19 +44,6 @@ static void hexdump(unsigned char *buf, int len)
|
|||
}
|
||||
#endif
|
||||
|
||||
#define MOUNT_ROOT_RDONLY 0x000
|
||||
#define RAMDISK_FLAGS 0x004
|
||||
#define ORIG_ROOT_DEV 0x008
|
||||
#define LOADER_TYPE 0x00c
|
||||
#define INITRD_START 0x010
|
||||
#define INITRD_SIZE 0x014
|
||||
#define COMMAND_LINE 0x100
|
||||
|
||||
#define RD_PROMPT (1<<15)
|
||||
#define RD_DOLOAD (1<<14)
|
||||
#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
|
||||
#define CMD_ARG_RD_DOLOAD "load_ramdisk="
|
||||
|
||||
#ifdef CONFIG_SH_SDRAM_OFFSET
|
||||
#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
|
||||
#else
|
||||
|
|
@ -94,13 +82,12 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
|
||||
return 1;
|
||||
|
||||
/* Setup parameters */
|
||||
memset(param, 0, size); /* Clear zero page */
|
||||
/* Clear zero page */
|
||||
memset(param, 0, size);
|
||||
|
||||
/* Set commandline */
|
||||
strcpy(cmdline, bootargs);
|
||||
|
||||
sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
|
||||
/* Initrd */
|
||||
if (images->rd_start || images->rd_end) {
|
||||
unsigned long ramdisk_flags = 0;
|
||||
|
|
@ -128,7 +115,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
|
||||
/* Boot kernel */
|
||||
kernel();
|
||||
/* does not return */
|
||||
|
||||
/* does not return */
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Renesas Solutions Corp.
|
||||
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Linux SuperH zImage loading and boot
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/zimage.h>
|
||||
|
||||
int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong (*zboot_entry)(int, char * const []) = NULL;
|
||||
char *s0, *s1;
|
||||
unsigned char *param = NULL;
|
||||
char *cmdline;
|
||||
char *bootargs;
|
||||
|
||||
disable_interrupts();
|
||||
|
||||
if (argc >= 3) {
|
||||
/* argv[1] holds the address of the zImage */
|
||||
s0 = argv[1];
|
||||
/* argv[2] holds the address of zero page */
|
||||
s1 = argv[2];
|
||||
} else {
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (s0)
|
||||
zboot_entry = (ulong (*)(int, char * const []))simple_strtoul(s0, NULL, 16);
|
||||
|
||||
/* empty_zero_page */
|
||||
if (s1)
|
||||
param = (unsigned char*)simple_strtoul(s1, NULL, 16);
|
||||
|
||||
/* Linux kernel command line */
|
||||
cmdline = (char *)param + COMMAND_LINE;
|
||||
bootargs = getenv("bootargs");
|
||||
|
||||
/* Clear zero page */
|
||||
memset(param, 0, 0x1000);
|
||||
|
||||
/* Set commandline */
|
||||
strcpy(cmdline, bootargs);
|
||||
|
||||
/* Boot */
|
||||
zboot_entry(0, NULL);
|
||||
|
||||
exit:
|
||||
return -1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
zimageboot, 3, 0, do_sh_zimageboot,
|
||||
"Boot zImage for Renesas SH",
|
||||
""
|
||||
);
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# Copyright (C) 2010 Nobuhiro Iwamatsu
|
||||
# Copyright (C) 2008 Renesas Solutions Corp.
|
||||
#
|
||||
# u-boot/board/shmin/Makefile
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).o
|
||||
|
||||
OBJS := shmin.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
LIB := $(addprefix $(obj),$(LIB))
|
||||
OBJS := $(addprefix $(obj),$(OBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# Copyright (C) 2010 Nobuhiro Iwamatsu
|
||||
#
|
||||
# u-boot/board/shmin/config.mk
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
|
||||
#
|
||||
# TEXT_BASE refers to image _after_ relocation.
|
||||
#
|
||||
# NOTE: Must match value used in u-boot.lds (in this directory).
|
||||
#
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x8DFB0000
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
|
||||
.global lowlevel_init
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
lowlevel_init:
|
||||
/* Use setting of original bootloader */
|
||||
rts
|
||||
nop
|
||||
.align 2
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright (C) 2007 - 2010
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* board/shmin/shmin.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("BOARD: T-SH7706LAN ");
|
||||
if(readb(0xb0008006) == 0xab)
|
||||
puts("v2\n");
|
||||
else
|
||||
puts("v1\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
writew(0x2980, BCR2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
|
||||
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void led_set_state(unsigned short value)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FLASH_CFI_LEGACY)
|
||||
#include <flash.h>
|
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
|
||||
{
|
||||
int sect[] = CONFIG_SYS_ATMEL_SECT;
|
||||
int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
|
||||
int i, j, k;
|
||||
|
||||
if (base != CONFIG_SYS_ATMEL_BASE)
|
||||
return 0;
|
||||
|
||||
info->flash_id = 0x01000000;
|
||||
info->portwidth = 1;
|
||||
info->chipwidth = 1;
|
||||
info->buffer_size = 1;
|
||||
info->erase_blk_tout = 16384;
|
||||
info->write_tout = 2;
|
||||
info->buffer_write_tout = 5;
|
||||
info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
|
||||
info->cmd_reset = 0x00F0;
|
||||
info->interface = FLASH_CFI_X8;
|
||||
info->legacy_unlock = 0;
|
||||
info->manufacturer_id = (u16) ATM_MANUFACT;
|
||||
info->device_id = ATM_ID_LV040;
|
||||
info->device_id2 = 0;
|
||||
info->ext_addr = 0;
|
||||
info->cfi_version = 0x3133;
|
||||
info->cfi_offset = 0x0000;
|
||||
info->addr_unlock1 = 0x00000555;
|
||||
info->addr_unlock2 = 0x000002AA;
|
||||
info->name = "CFI conformant";
|
||||
info->size = 0;
|
||||
info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
|
||||
info->start[0] = base;
|
||||
|
||||
for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
|
||||
info->size += sect[i] * sectsz[i];
|
||||
for (j = 0; j < sect[i]; j++, k++) {
|
||||
info->start[k + 1] = info->start[k] + sectsz[i];
|
||||
info->protect[k] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_FLASH_CFI_LEGACY */
|
||||
|
|
@ -745,6 +745,7 @@ xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx
|
|||
rsk7203 sh sh2 rsk7203 renesas -
|
||||
mpr2 sh sh3 mpr2 - -
|
||||
ms7720se sh sh3 ms7720se - -
|
||||
shmin sh sh3 shmin - -
|
||||
espt sh sh4 espt - -
|
||||
ms7722se sh sh4 ms7722se - -
|
||||
ms7750se sh sh4 ms7750se - -
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* SuperH SCIF device driver.
|
||||
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu
|
||||
* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
|
||||
* Copyright (C) 2002 - 2008 Paul Mundt
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -20,8 +21,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#include "serial_sh.h"
|
||||
|
||||
#if defined(CONFIG_CONS_SCIF0)
|
||||
# define SCIF_BASE SCIF0_BASE
|
||||
|
|
@ -39,139 +39,88 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
# error "Default SCIF doesn't set....."
|
||||
#endif
|
||||
|
||||
/* Base register */
|
||||
#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
|
||||
#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
|
||||
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
|
||||
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
|
||||
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
|
||||
#if defined(CONFIG_CPU_SH7720) || \
|
||||
(defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
|
||||
# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
|
||||
# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
|
||||
#if defined(CONFIG_SCIF_A)
|
||||
#define SCIF_BASE_PORT PORT_SCIFA
|
||||
#else
|
||||
# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
|
||||
# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
|
||||
#define SCIF_BASE_PORT PORT_SCIF
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785)
|
||||
# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
|
||||
# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0xFF
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
# if defined(CONFIG_CONS_SCIF2)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
# else
|
||||
# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
|
||||
# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0xFF
|
||||
# endif
|
||||
#elif defined(CONFIG_CPU_SH7723)
|
||||
# if defined(CONFIG_SCIF_A)
|
||||
# define SCLSR SCFSR
|
||||
# define LSR_ORER 0x0200
|
||||
# define FIFOLEVEL_MASK 0x3F
|
||||
#else
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#endif
|
||||
#elif defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7722) || \
|
||||
defined(CONFIG_CPU_SH7203)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#elif defined(CONFIG_CPU_SH7720)
|
||||
# define SCLSR SCFSR
|
||||
# define LSR_ORER 0x0200
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#elif defined(CONFIG_CPU_SH7710) || \
|
||||
defined(CONFIG_CPU_SH7712)
|
||||
# define SCLSR SCFSR /* SCSSR */
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#endif
|
||||
|
||||
/* SCBRR register value setting */
|
||||
#if defined(CONFIG_CPU_SH7720)
|
||||
# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
|
||||
#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
|
||||
/* SH7723 SCIFA use bus clock. So clock *2 */
|
||||
# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
|
||||
#else /* Generic SuperH */
|
||||
# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
|
||||
#endif
|
||||
|
||||
#define SCR_RE (1 << 4)
|
||||
#define SCR_TE (1 << 5)
|
||||
#define FCR_RFRST (1 << 1) /* RFCL */
|
||||
#define FCR_TFRST (1 << 2) /* TFCL */
|
||||
#define FSR_DR (1 << 0)
|
||||
#define FSR_RDF (1 << 1)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_BRK (1 << 4)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_TEND (1 << 6)
|
||||
#define FSR_ER (1 << 7)
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
static struct uart_port sh_sci = {
|
||||
.membase = (unsigned char*)SCIF_BASE,
|
||||
.mapbase = SCIF_BASE,
|
||||
.type = SCIF_BASE_PORT,
|
||||
};
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
|
||||
}
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
writew((SCR_RE | SCR_TE), SCSCR);
|
||||
writew(0, SCSMR);
|
||||
writew(0, SCSMR);
|
||||
writew((FCR_RFRST | FCR_TFRST), SCFCR);
|
||||
readw(SCFCR);
|
||||
writew(0, SCFCR);
|
||||
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
|
||||
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
|
||||
sci_out(&sh_sci, SCSMR, 0);
|
||||
sci_out(&sh_sci, SCSMR, 0);
|
||||
sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
|
||||
sci_in(&sh_sci, SCFCR);
|
||||
sci_out(&sh_sci, SCFCR, 0);
|
||||
|
||||
serial_setbrg();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SH7760) || \
|
||||
defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785) || \
|
||||
defined(CONFIG_CPU_SH7786)
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCRFDR) & 0xff;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
if ((port->mapbase == 0xffe00000) ||
|
||||
(port->mapbase == 0xffe08000)) {
|
||||
/* SCIF0/1*/
|
||||
return sci_in(port, SCRFDR) & 0xff;
|
||||
} else {
|
||||
/* SCIF2 */
|
||||
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_ARCH_SH7372)
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
if (port->type == PORT_SCIFA)
|
||||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
else
|
||||
return sci_in(port, SCRFDR);
|
||||
}
|
||||
#else
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int serial_rx_fifo_level(void)
|
||||
{
|
||||
#if defined(SCRFDR)
|
||||
return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK;
|
||||
#else
|
||||
return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK;
|
||||
#endif
|
||||
return scif_rxfill(&sh_sci);
|
||||
}
|
||||
|
||||
void serial_raw_putc(const char c)
|
||||
{
|
||||
unsigned int fsr_bits_to_clear;
|
||||
|
||||
while (1) {
|
||||
if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */
|
||||
fsr_bits_to_clear = FSR_TEND;
|
||||
/* Tx fifo is empty */
|
||||
if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
writeb(c, SCFTDR);
|
||||
if (fsr_bits_to_clear != 0)
|
||||
writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR);
|
||||
sci_out(&sh_sci, SCxTDR, c);
|
||||
sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
|
|
@ -193,27 +142,25 @@ int serial_tstc(void)
|
|||
return serial_rx_fifo_level() ? 1 : 0;
|
||||
}
|
||||
|
||||
#define FSR_ERR_CLEAR 0x0063
|
||||
#define RDRF_CLEAR 0x00fc
|
||||
void handle_error(void)
|
||||
{
|
||||
readw(SCFSR);
|
||||
writew(FSR_ERR_CLEAR, SCFSR);
|
||||
readw(SCLSR);
|
||||
writew(0x00, SCLSR);
|
||||
sci_in(&sh_sci, SCxSR);
|
||||
sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
|
||||
sci_in(&sh_sci, SCLSR);
|
||||
sci_out(&sh_sci, SCLSR, 0x00);
|
||||
}
|
||||
|
||||
int serial_getc_check(void)
|
||||
{
|
||||
unsigned short status;
|
||||
|
||||
status = readw(SCFSR);
|
||||
status = sci_in(&sh_sci, SCxSR);
|
||||
|
||||
if (status & (FSR_FER | FSR_ER | FSR_BRK))
|
||||
if (status & SCIF_ERRORS)
|
||||
handle_error();
|
||||
if (readw(SCLSR) & LSR_ORER)
|
||||
if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
|
||||
handle_error();
|
||||
return status & (FSR_DR | FSR_RDF);
|
||||
return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
|
|
@ -224,16 +171,15 @@ int serial_getc(void)
|
|||
while (!serial_getc_check())
|
||||
;
|
||||
|
||||
ch = readb(SCFRDR);
|
||||
status = readw(SCFSR);
|
||||
ch = sci_in(&sh_sci, SCxRDR);
|
||||
status = sci_in(&sh_sci, SCxSR);
|
||||
|
||||
writew(RDRF_CLEAR, SCFSR);
|
||||
sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
|
||||
|
||||
if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
|
||||
if (status & SCIF_ERRORS)
|
||||
handle_error();
|
||||
|
||||
if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
|
||||
handle_error();
|
||||
|
||||
if (readw(SCLSR) & LSR_ORER)
|
||||
handle_error();
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,690 @@
|
|||
/*
|
||||
* Copy and modify from linux/drivers/serial/sh-sci.h
|
||||
*/
|
||||
|
||||
struct uart_port {
|
||||
unsigned long iobase; /* in/out[bwl] */
|
||||
unsigned char *membase; /* read/write[bwl] */
|
||||
unsigned long mapbase; /* for ioremap */
|
||||
unsigned int type; /* port type */
|
||||
};
|
||||
|
||||
#define PORT_SCI 52
|
||||
#define PORT_SCIF 53
|
||||
#define PORT_SCIFA 83
|
||||
#define PORT_SCIFB 93
|
||||
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
#include <asm/regs306x.h>
|
||||
#endif
|
||||
#if defined(CONFIG_H8S2678)
|
||||
#include <asm/regs267x.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7706) || \
|
||||
defined(CONFIG_CPU_SH7707) || \
|
||||
defined(CONFIG_CPU_SH7708) || \
|
||||
defined(CONFIG_CPU_SH7709)
|
||||
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
|
||||
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7705)
|
||||
# define SCIF0 0xA4400000
|
||||
# define SCIF2 0xA4410000
|
||||
# define SCSMR_Ir 0xA44A0000
|
||||
# define IRDA_SCIF SCIF0
|
||||
# define SCPCR 0xA4000116
|
||||
# define SCPDR 0xA4000136
|
||||
|
||||
/* Set the clock source,
|
||||
* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
|
||||
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
|
||||
*/
|
||||
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
|
||||
#elif defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define PORT_PTCR 0xA405011EUL
|
||||
# define PORT_PVCR 0xA4050122UL
|
||||
# define SCIF_ORER 0x0200 /* overrun error bit */
|
||||
#elif defined(CONFIG_SH_RTS7751R2D)
|
||||
# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7750R) || \
|
||||
defined(CONFIG_CPU_SH7750S) || \
|
||||
defined(CONFIG_CPU_SH7091) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7751R)
|
||||
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
|
||||
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
|
||||
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
|
||||
#elif defined(CONFIG_CPU_SH7760)
|
||||
# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
|
||||
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define PACR 0xa4050100
|
||||
# define PBCR 0xa4050102
|
||||
# define SCSCR_INIT(port) 0x3B
|
||||
#elif defined(CONFIG_CPU_SH7343)
|
||||
# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7722)
|
||||
# define PADR 0xA4050120
|
||||
# undef PSDR
|
||||
# define PSDR 0xA405013e
|
||||
# define PWDR 0xA4050166
|
||||
# define PSCR 0xA405011E
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7366)
|
||||
# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
|
||||
# define SCSPTR0 SCPDR0
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7723)
|
||||
# define SCSPTR0 0xa4050160
|
||||
# define SCSPTR1 0xa405013e
|
||||
# define SCSPTR2 0xa4050160
|
||||
# define SCSPTR3 0xa405013e
|
||||
# define SCSPTR4 0xa4050128
|
||||
# define SCSPTR5 0xa4050128
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7724)
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
|
||||
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
|
||||
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
|
||||
#elif defined(CONFIG_CPU_SH4_202)
|
||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
|
||||
# define SCIF_BASE_ADDR 0x01030000
|
||||
# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
|
||||
# define SCIF_PTR2_OFFS 0x0000020
|
||||
# define SCIF_LSR2_OFFS 0x0000024
|
||||
# define SCSPTR\
|
||||
((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCLSR2\
|
||||
((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
|
||||
#elif defined(CONFIG_H8S2678)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
|
||||
#elif defined(CONFIG_CPU_SH7757)
|
||||
# define SCSPTR0 0xfe4b0020
|
||||
# define SCSPTR1 0xfe4b0020
|
||||
# define SCSPTR2 0xfe4b0020
|
||||
# define SCIF_ORER 0x0001
|
||||
# define SCSCR_INIT(port) 0x38
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7770)
|
||||
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xff925020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
|
||||
#elif defined(CONFIG_CPU_SH7780)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
|
||||
#if defined(CONFIG_SH_SH2007)
|
||||
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
|
||||
# define SCSCR_INIT(port) 0x38
|
||||
#else
|
||||
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
|
||||
# define SCSCR_INIT(port) 0x3a
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_CPU_SH7785) || \
|
||||
defined(CONFIG_CPU_SH7786)
|
||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
|
||||
# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
|
||||
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7201) || \
|
||||
defined(CONFIG_CPU_SH7203) || \
|
||||
defined(CONFIG_CPU_SH7206) || \
|
||||
defined(CONFIG_CPU_SH7263)
|
||||
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
|
||||
# if defined(CONFIG_CPU_SH7201)
|
||||
# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
|
||||
# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
|
||||
# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
|
||||
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
|
||||
# endif
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7619)
|
||||
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SHX3)
|
||||
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#else
|
||||
# error CPU subtype not defined
|
||||
#endif
|
||||
|
||||
/* SCSCR */
|
||||
#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
|
||||
#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
|
||||
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
|
||||
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
|
||||
#if defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7091) || \
|
||||
defined(CONFIG_CPU_SH7750R) || \
|
||||
defined(CONFIG_CPU_SH7722) || \
|
||||
defined(CONFIG_CPU_SH7750S) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7751R) || \
|
||||
defined(CONFIG_CPU_SH7763) || \
|
||||
defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785) || \
|
||||
defined(CONFIG_CPU_SH7786) || \
|
||||
defined(CONFIG_CPU_SHX3)
|
||||
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
|
||||
#elif defined(CONFIG_CPU_SH7724)
|
||||
#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
|
||||
#else
|
||||
#define SCI_CTRL_FLAGS_REIE 0
|
||||
#endif
|
||||
/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
|
||||
/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
|
||||
|
||||
/* SCxSR SCI */
|
||||
#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
|
||||
#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
|
||||
|
||||
/* SCxSR SCIF */
|
||||
#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
# define SCIF_ORER 0x0200
|
||||
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
# define SCIF_TXROOM_MAX 64
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
# define SCIF_TXROOM_MAX 64
|
||||
/* SH7763 SCIF2 support */
|
||||
# define SCIF2_RFDC_MASK 0x001f
|
||||
# define SCIF2_TXROOM_MAX 16
|
||||
#else
|
||||
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
|
||||
# define SCIF_RFDC_MASK 0x001f
|
||||
# define SCIF_TXROOM_MAX 16
|
||||
#endif
|
||||
|
||||
#ifndef SCIF_ORER
|
||||
#define SCIF_ORER 0x0000
|
||||
#endif
|
||||
|
||||
#define SCxSR_TEND(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
||||
#define SCxSR_ERRORS(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
||||
#define SCxSR_RDxF(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
||||
#define SCxSR_TDxE(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
||||
#define SCxSR_FER(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
||||
#define SCxSR_PER(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
||||
#define SCxSR_BRK(port)\
|
||||
((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
||||
#define SCxSR_ORER(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
||||
# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
|
||||
#else
|
||||
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
|
||||
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
|
||||
# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
|
||||
#endif
|
||||
|
||||
/* SCFCR */
|
||||
#define SCFCR_RFRST 0x0002
|
||||
#define SCFCR_TFRST 0x0004
|
||||
#define SCFCR_TCRST 0x4000
|
||||
#define SCFCR_MCE 0x0008
|
||||
|
||||
#define SCI_MAJOR 204
|
||||
#define SCI_MINOR_START 8
|
||||
|
||||
/* Generic serial flags */
|
||||
#define SCI_RX_THROTTLE 0x0000001
|
||||
|
||||
#define SCI_MAGIC 0xbabeface
|
||||
|
||||
/*
|
||||
* Events are used to schedule things to happen at timer-interrupt
|
||||
* time, instead of at rs interrupt time.
|
||||
*/
|
||||
#define SCI_EVENT_WRITE_WAKEUP 0
|
||||
|
||||
#define SCI_IN(size, offset)\
|
||||
if ((size) == 8) {\
|
||||
return readb(port->membase + (offset));\
|
||||
} else {\
|
||||
return readw(port->membase + (offset));\
|
||||
}
|
||||
#define SCI_OUT(size, offset, value)\
|
||||
if ((size) == 8) {\
|
||||
writeb(value, port->membase + (offset));\
|
||||
} else if ((size) == 16) {\
|
||||
writew(value, port->membase + (offset));\
|
||||
}
|
||||
|
||||
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
||||
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
|
||||
SCI_IN(scif_size, scif_offset)\
|
||||
} else { /* PORT_SCI or PORT_SCIFA */\
|
||||
SCI_IN(sci_size, sci_offset);\
|
||||
}\
|
||||
}\
|
||||
static inline void sci_##name##_out(struct uart_port *port,\
|
||||
unsigned int value) {\
|
||||
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
|
||||
SCI_OUT(scif_size, scif_offset, value)\
|
||||
} else { /* PORT_SCI or PORT_SCIFA */\
|
||||
SCI_OUT(sci_size, sci_offset, value);\
|
||||
}\
|
||||
}
|
||||
|
||||
#ifdef CONFIG_H8300
|
||||
/* h8300 don't have SCIF */
|
||||
#define CPU_SCIF_FNS(name) \
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
||||
return 0;\
|
||||
}\
|
||||
static inline void sci_##name##_out(struct uart_port *port,\
|
||||
unsigned int value) {\
|
||||
}
|
||||
#else
|
||||
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
||||
SCI_IN(scif_size, scif_offset);\
|
||||
}\
|
||||
static inline void sci_##name##_out(struct uart_port *port,\
|
||||
unsigned int value) {\
|
||||
SCI_OUT(scif_size, scif_offset, value);\
|
||||
}
|
||||
#endif
|
||||
|
||||
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
||||
SCI_IN(sci_size, sci_offset);\
|
||||
}\
|
||||
static inline void sci_##name##_out(struct uart_port *port,\
|
||||
unsigned int value) {\
|
||||
SCI_OUT(sci_size, sci_offset, value);\
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SH3) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, \
|
||||
sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
|
||||
sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#elif defined(CONFIG_ARCH_SH7372)
|
||||
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
||||
sh4_scifb_offset, sh4_scifb_size) \
|
||||
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
||||
sh4_scifb_offset, sh4_scifb_size)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#else
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh3_scif_offset, sh3_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
|
||||
#endif
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name)
|
||||
#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
|
||||
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
||||
sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#else
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
|
||||
sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377)
|
||||
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
SCIF_FNS(SCBRR, 0x04, 8)
|
||||
SCIF_FNS(SCSCR, 0x08, 16)
|
||||
SCIF_FNS(SCTDSR, 0x0c, 8)
|
||||
SCIF_FNS(SCFER, 0x10, 16)
|
||||
SCIF_FNS(SCxSR, 0x14, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCxTDR, 0x20, 8)
|
||||
SCIF_FNS(SCxRDR, 0x24, 8)
|
||||
SCIF_FNS(SCLSR, 0x00, 0)
|
||||
#elif defined(CONFIG_ARCH_SH7372)
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
SCIF_FNS(SCBRR, 0x04, 8)
|
||||
SCIF_FNS(SCSCR, 0x08, 16)
|
||||
SCIF_FNS(SCTDSR, 0x0c, 16)
|
||||
SCIF_FNS(SCFER, 0x10, 16)
|
||||
SCIF_FNS(SCxSR, 0x14, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCTFDR, 0x38, 16)
|
||||
SCIF_FNS(SCRFDR, 0x3c, 16)
|
||||
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
|
||||
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
|
||||
SCIF_FNS(SCLSR, 0x00, 0)
|
||||
#elif defined(CONFIG_CPU_SH7723) ||\
|
||||
defined(CONFIG_CPU_SH7724)
|
||||
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
|
||||
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
|
||||
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
|
||||
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
|
||||
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
|
||||
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
|
||||
SCIx_FNS(SCSPTR, 0, 0, 0, 0)
|
||||
SCIF_FNS(SCTDSR, 0x0c, 8)
|
||||
SCIF_FNS(SCFER, 0x10, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCLSR, 0x24, 16)
|
||||
#else
|
||||
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
|
||||
/* name off sz off sz off sz off sz off sz*/
|
||||
SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
|
||||
SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
|
||||
SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
|
||||
SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
|
||||
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
||||
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
||||
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
||||
#if defined(CONFIG_CPU_SH7760) || \
|
||||
defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785) || \
|
||||
defined(CONFIG_CPU_SH7786)
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
|
||||
SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
|
||||
SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
||||
#else
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
#if defined(CONFIG_CPU_SH7722)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
|
||||
#else
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
|
||||
#endif
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
||||
#endif
|
||||
#endif
|
||||
#define sci_in(port, reg) sci_##reg##_in(port)
|
||||
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
|
||||
|
||||
/* H8/300 series SCI pins assignment */
|
||||
#if defined(__H8300H__) || defined(__H8300S__)
|
||||
static const struct __attribute__((packed)) {
|
||||
int port; /* GPIO port no */
|
||||
unsigned short rx, tx; /* GPIO bit no */
|
||||
} h8300_sci_pins[] = {
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
{ /* SCI0 */
|
||||
.port = H8300_GPIO_P9,
|
||||
.rx = H8300_GPIO_B2,
|
||||
.tx = H8300_GPIO_B0,
|
||||
},
|
||||
{ /* SCI1 */
|
||||
.port = H8300_GPIO_P9,
|
||||
.rx = H8300_GPIO_B3,
|
||||
.tx = H8300_GPIO_B1,
|
||||
},
|
||||
{ /* SCI2 */
|
||||
.port = H8300_GPIO_PB,
|
||||
.rx = H8300_GPIO_B7,
|
||||
.tx = H8300_GPIO_B6,
|
||||
}
|
||||
#elif defined(CONFIG_H8S2678)
|
||||
{ /* SCI0 */
|
||||
.port = H8300_GPIO_P3,
|
||||
.rx = H8300_GPIO_B2,
|
||||
.tx = H8300_GPIO_B0,
|
||||
},
|
||||
{ /* SCI1 */
|
||||
.port = H8300_GPIO_P3,
|
||||
.rx = H8300_GPIO_B3,
|
||||
.tx = H8300_GPIO_B1,
|
||||
},
|
||||
{ /* SCI2 */
|
||||
.port = H8300_GPIO_P5,
|
||||
.rx = H8300_GPIO_B1,
|
||||
.tx = H8300_GPIO_B0,
|
||||
}
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7706) || \
|
||||
defined(CONFIG_CPU_SH7707) || \
|
||||
defined(CONFIG_CPU_SH7708) || \
|
||||
defined(CONFIG_CPU_SH7709)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfffffe80)
|
||||
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7751R) || \
|
||||
defined(CONFIG_CPU_SH7750R) || \
|
||||
defined(CONFIG_CPU_SH7750S) || \
|
||||
defined(CONFIG_CPU_SH7091)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
int ch = (port->mapbase - SMR0) >> 3;
|
||||
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
|
||||
}
|
||||
#else /* default case for non-SCI processors */
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values for the BitRate Register (SCBRR)
|
||||
*
|
||||
* The values are actually divisors for a frequency which can
|
||||
* be internal to the SH3 (14.7456MHz) or derived from an external
|
||||
* clock source. This driver assumes the internal clock is used;
|
||||
* to support using an external clock source, config options or
|
||||
* possibly command-line options would need to be added.
|
||||
*
|
||||
* Also, to support speeds below 2400 (why?) the lower 2 bits of
|
||||
* the SCSMR register would also need to be set to non-zero values.
|
||||
*
|
||||
* -- Greg Banks 27Feb2000
|
||||
*
|
||||
* Answer: The SCBRR register is only eight bits, and the value in
|
||||
* it gets larger with lower baud rates. At around 2400 (depending on
|
||||
* the peripherial module clock) you run out of bits. However the
|
||||
* lower two bits of SCSMR allow the module clock to be divided down,
|
||||
* scaling the value which is needed in SCBRR.
|
||||
*
|
||||
* -- Stuart Menefy - 23 May 2000
|
||||
*
|
||||
* I meant, why would anyone bother with bitrates below 2400.
|
||||
*
|
||||
* -- Greg Banks - 7Jul2000
|
||||
*
|
||||
* You "speedist"! How will I use my 110bps ASR-33 teletype with paper
|
||||
* tape reader as a console!
|
||||
*
|
||||
* -- Mitch Davis - 15 Jul 2000
|
||||
*/
|
||||
|
||||
#if (defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785) || \
|
||||
defined(CONFIG_CPU_SH7786)) && \
|
||||
!defined(CONFIG_SH_SH2007)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SH7723) ||\
|
||||
defined(CONFIG_CPU_SH7724)
|
||||
static inline int scbrr_calc(struct uart_port port, int bps, int clk)
|
||||
{
|
||||
if (port.type == PORT_SCIF)
|
||||
return (clk+16*bps)/(32*bps)-1;
|
||||
else
|
||||
return ((clk*2)+16*bps)/(16*bps)-1;
|
||||
}
|
||||
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
|
||||
#else /* Generic SH */
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
|
||||
#endif
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_SH_ZIMAGEBOOT
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE 1
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_SH_ZIMAGEBOOT
|
||||
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
|
|
|||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
|
||||
*
|
||||
* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SHMIN_H
|
||||
#define __SHMIN_H
|
||||
|
||||
#define CONFIG_SH 1
|
||||
#define CONFIG_SH3 1
|
||||
#define CONFIG_CPU_SH7706 1
|
||||
/* T-SH7706LAN */
|
||||
#define CONFIG_SHMIN 1
|
||||
/* T-SH7706LSR*/
|
||||
/* #define CONFIG_T_SH7706LSR 1 */
|
||||
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTARGS "console=ttySC0,115200"
|
||||
|
||||
/*
|
||||
* This board has original boot loader. If you write u-boot to 0x0,
|
||||
* you should set undef.
|
||||
*/
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* system */
|
||||
#define SHMIN_SDRAM_BASE (0x8C000000)
|
||||
#define SHMIN_FLASH_BASE_1 (0xA0000000)
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
|
||||
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
|
||||
/* Buffer size for Boot Arguments passed to kernel */
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
/* List of legal baudrate settings for this board */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE 1
|
||||
#define CONFIG_CONS_SCIF0 1
|
||||
|
||||
/* memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE
|
||||
#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 256
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 11
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
|
||||
#define CONFIG_FLASH_CFI_LEGACY
|
||||
#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT
|
||||
#define CONFIG_SYS_ATMEL_REGION 4
|
||||
#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
|
||||
#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
|
||||
#ifdef CONFIG_T_SH7706LSR
|
||||
#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000)
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
|
||||
|
||||
/* Board Clock */
|
||||
#ifdef CONFIG_T_SH7706LSR
|
||||
#define CONFIG_SYS_CLK_FREQ 40000000
|
||||
#else
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif /* CONFIG_T_SH7706LSR */
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Network device */
|
||||
#define CONFIG_DRIVER_NE2000
|
||||
#define CONFIG_DRIVER_NE2000_BASE (0xb0000300)
|
||||
|
||||
#endif /* __SHMIN_H */
|
||||
Loading…
Reference in New Issue