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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 

Zap the useless addr variable.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-21 05:29:05 +02:00
parent c8570afa04
commit c654087206
1 changed files with 2 additions and 3 deletions
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5
drivers/ddr/altera/sequencer.c
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@ -2977,7 +2977,6 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
int i;
u32 sticky_bit_chk;
u32 min_index;
u32 addr;
int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
int mid;
@ -2996,8 +2995,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
dm_margin = 0;
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
start_dqs = readl(addr +
start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_IO_OUT1_DELAY_OFFSET) +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
/* Per-bit deskew. */