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video: mb862xx: improve board-specific Lime configuration 

To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
This commit is contained in:
Wolfgang Grandegger 2009-10-23 12:03:13 +02:00 committed by Anatolij Gustschin
parent f2b4bc04d6
commit c28d3bbe96
6 changed files with 54 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
board/lwmon5/lwmon5.c
View File

@ -532,13 +532,6 @@ unsigned int board_video_init (void)
udelay(500); udelay(500);
gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
/* Lime memory clock adjusted to 100MHz */
out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
mb862xx.winSizeX = 640; mb862xx.winSizeX = 640;
mb862xx.winSizeY = 480; mb862xx.winSizeY = 480;
mb862xx.gdfBytesPP = 2; mb862xx.gdfBytesPP = 2;

46
board/socrates/socrates.c
View File

@ -268,17 +268,6 @@ ft_board_setup(void *blob, bd_t *bd)
} }
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
/* Lime clock frequency */
#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000
#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000
/* SDRAM parameter */
#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63
#define DISPLAY_WIDTH 800
#define DISPLAY_HEIGHT 480
#define DEFAULT_BRIGHTNESS 25 #define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31) #define BACKLIGHT_ENABLE (1 << 31)
@ -308,14 +297,12 @@ const gdc_regs *board_get_regs (void)
return init_regs; return init_regs;
} }
#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
int lime_probe(void) int lime_probe(void)
{ {
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2; uint cfg_br2;
uint cfg_or2; uint cfg_or2;
uint reg; int type;
cfg_br2 = memctl->br2; cfg_br2 = memctl->br2;
cfg_or2 = memctl->or2; cfg_or2 = memctl->or2;
@ -325,21 +312,15 @@ int lime_probe(void)
memctl->or2 = 0xfc000410; memctl->or2 = 0xfc000410;
memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
/* Try to access GDC ID/Revision registers */ /* Get controller type */
reg = in_be32((void *)CONFIG_SYS_LIME_CID); type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
reg = in_be32((void *)CONFIG_SYS_LIME_CID);
if (reg == 0x303) {
reg = in_be32((void *)CONFIG_SYS_LIME_REV);
reg = in_be32((void *)CONFIG_SYS_LIME_REV);
reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
} else
reg = 0;
/* Restore previous CS2 configuration */ /* Restore previous CS2 configuration */
memctl->br2 = 0; memctl->br2 = 0;
memctl->or2 = cfg_or2; memctl->or2 = cfg_or2;
memctl->br2 = cfg_br2; memctl->br2 = cfg_br2;
return reg;
return (type == MB862XX_TYPE_LIME) ? 1 : 0;
} }
/* Returns Lime base address */ /* Returns Lime base address */
@ -348,21 +329,8 @@ unsigned int board_video_init (void)
if (!lime_probe()) if (!lime_probe())
return 0; return 0;
/* mb862xx.winSizeX = 800;
* Reset Lime controller mb862xx.winSizeY = 480;
*/
out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
udelay(200);
/* Set Lime clock to 133MHz */
out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
/* Delay required */
udelay(300);
/* Set memory parameters */
out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
mb862xx.winSizeX = DISPLAY_WIDTH;
mb862xx.winSizeY = DISPLAY_HEIGHT;
mb862xx.gdfIndex = GDF_15BIT_555RGB; mb862xx.gdfIndex = GDF_15BIT_555RGB;
mb862xx.gdfBytesPP = 2; mb862xx.gdfBytesPP = 2;

34
drivers/video/mb862xx.c
View File

@ -340,6 +340,30 @@ unsigned int card_init (void)
} }
#endif #endif
#if !defined(CONFIG_VIDEO_CORALP)
int mb862xx_probe(unsigned int addr)
{
GraphicDevice *dev = &mb862xx;
unsigned int reg;
dev->frameAdrs = addr;
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Try to access GDC ID/Revision registers */
reg = HOST_RD_REG (GC_CID);
reg = HOST_RD_REG (GC_CID);
if (reg == 0x303) {
reg = DE_RD_REG(GC_REV);
reg = DE_RD_REG(GC_REV);
if ((reg & ~0xff) == 0x20050100)
return MB862XX_TYPE_LIME;
}
return 0;
}
#endif
void *video_hw_init (void) void *video_hw_init (void)
{ {
GraphicDevice *dev = &mb862xx; GraphicDevice *dev = &mb862xx;
@ -359,8 +383,16 @@ void *video_hw_init (void)
if ((dev->frameAdrs = board_video_init ()) == 0) { if ((dev->frameAdrs = board_video_init ()) == 0) {
puts ("Controller not found!\n"); puts ("Controller not found!\n");
return NULL; return NULL;
} else } else {
puts ("Lime\n"); puts ("Lime\n");
/* Set Change of Clock Frequency Register */
HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
/* Delay required */
udelay(300);
/* Set Memory I/F Mode Register) */
HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
}
#endif #endif
de_init (); de_init ();

10
include/configs/lwmon5.h
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@ -495,8 +495,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Graphics (Fujitsu Lime) * Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
/* Lime Clock frequency is to set 100MHz */ /* Lime Clock frequency is to set 100MHz */
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
#if 0 #if 0
@ -504,15 +502,15 @@
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
#endif #endif
/* SDRAM Parameter register */
#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
and pixel flare on display when 133MHz was configured. According to and pixel flare on display when 133MHz was configured. According to
SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
#else #else
#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
#endif #endif
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------

5
include/configs/socrates.h
View File

@ -210,6 +210,11 @@
#define CONFIG_VIDEO_BMP_GZIP #define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
#define CONFIG_SYS_MB862xx_CCF 0x10000
/* SDRAM parameter */
#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
/* Serial Port */ /* Serial Port */
#define CONFIG_CONS_INDEX 1 #define CONFIG_CONS_INDEX 1

5
include/mb862xx.h
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@ -32,6 +32,8 @@
#define PCI_DEVICE_ID_CORAL_P 0x2019 #define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E #define PCI_DEVICE_ID_CORAL_PA 0x201E
#define MB862XX_TYPE_LIME 0x1
#define GC_HOST_BASE 0x01fc0000 #define GC_HOST_BASE 0x01fc0000
#define GC_DISP_BASE 0x01fd0000 #define GC_DISP_BASE 0x01fd0000
#define GC_DRAW_BASE 0x01ff0000 #define GC_DRAW_BASE 0x01ff0000
@ -39,6 +41,7 @@
/* Host interface registers */ /* Host interface registers */
#define GC_SRST 0x0000002c #define GC_SRST 0x0000002c
#define GC_CCF 0x00000038 #define GC_CCF 0x00000038
#define GC_CID 0x000000f0
#define GC_MMR 0x0000fffc #define GC_MMR 0x0000fffc
/* /*
@ -99,6 +102,7 @@
#define GC_FC 0x00000480 #define GC_FC 0x00000480
#define GC_BC 0x00000484 #define GC_BC 0x00000484
#define GC_FIFO 0x000004a0 #define GC_FIFO 0x000004a0
#define GC_REV 0x00008084
#define GC_GEO_FIFO 0x00008400 #define GC_GEO_FIFO 0x00008400
typedef struct { typedef struct {
@ -106,6 +110,7 @@ typedef struct {
unsigned int value; unsigned int value;
} gdc_regs; } gdc_regs;
int mb862xx_probe(unsigned int addr);
const gdc_regs *board_get_regs (void); const gdc_regs *board_get_regs (void);
unsigned int board_video_init (void); unsigned int board_video_init (void);
void board_backlight_switch(int); void board_backlight_switch(int);