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Merge branch 'master' of http://git.denx.de/u-boot-sunxi

This commit is contained in:
Tom Rini 2016-10-12 08:30:46 -04:00
parent 3c594d34c4 55cdcdaad3
commit c14d4b0051
3 changed files with 45 additions and 23 deletions
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64
arch/arm/mach-sunxi/dram_sun8i_h3.c
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@ -217,35 +217,57 @@ static void mctl_zq_calibration(struct dram_para *para)
struct sunxi_mctl_ctl_reg * const mctl_ctl = struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
int i; if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
u16 zq_val[6]; (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
u8 val; u32 reg_val;
writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
CONFIG_DRAM_ZQ & 0xffff);
for (i = 0; i < 6; i++) {
u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
writel((zq << 20) | (zq << 16) | (zq << 12) |
(zq << 8) | (zq << 4) | (zq << 0),
&mctl_ctl->zqcr);
writel(PIR_CLRSR, &mctl_ctl->pir); writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL); mctl_phy_init(PIR_ZCAL);
zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; reg_val = readl(&mctl_ctl->zqdr[0]);
writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); reg_val &= (0x1f << 16) | (0x1f << 0);
reg_val |= reg_val << 8;
writel(reg_val, &mctl_ctl->zqdr[0]);
writel(PIR_CLRSR, &mctl_ctl->pir); reg_val = readl(&mctl_ctl->zqdr[1]);
mctl_phy_init(PIR_ZCAL); reg_val &= (0x1f << 16) | (0x1f << 0);
reg_val |= reg_val << 8;
writel(reg_val, &mctl_ctl->zqdr[1]);
writel(reg_val, &mctl_ctl->zqdr[2]);
} else {
int i;
u16 zq_val[6];
u8 val;
val = readl(&mctl_ctl->zqdr[0]) >> 24; writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
for (i = 0; i < 6; i++) {
u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
writel((zq << 20) | (zq << 16) | (zq << 12) |
(zq << 8) | (zq << 4) | (zq << 0),
&mctl_ctl->zqcr);
writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL);
zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL);
val = readl(&mctl_ctl->zqdr[0]) >> 24;
zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
}
writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
} }
writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
} }
static void mctl_set_cr(struct dram_para *para) static void mctl_set_cr(struct dram_para *para)

2
configs/A20-OLinuXino-Lime2_defconfig
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@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480 CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17" CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_VBUS_DET="PH5"

2
configs/A20-OLinuXino-Lime_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480 CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set