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Minor code cleanup

This commit is contained in:
Wolfgang Denk 2006-03-06 13:03:37 +01:00
parent 4e3ccd2692
commit bfc81252c0
24 changed files with 433 additions and 529 deletions
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2
CHANGELOG
View File

@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Minor code cleanup
* Merge the new NAND code (testing-NAND brach); see doc/README.nand
Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005

1
board/amcc/bamboo/config.mk
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@ -35,4 +35,3 @@ endif
# legacy nand support
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

1
board/bmw/config.mk
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@ -30,4 +30,3 @@ TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
-DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\
-DTEXT_BASE=$(TEXT_BASE)

1
board/dave/PPChameleonEVB/config.mk
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@ -32,4 +32,3 @@ BOARDLIBS = drivers/nand/libnand.a
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

3
board/esd/common/auto_update.c
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@ -42,9 +42,6 @@
#error "must define CFG_CMD_FAT"
#endif
extern au_image_t au_image[];
extern int N_AU_IMAGES;

1
board/esd/common/cmd_loadpci.c
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@ -120,4 +120,3 @@ U_BOOT_CMD(
);
#endif

1
board/esd/cpci405/config.mk
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@ -41,4 +41,3 @@ endif
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

1
board/esd/cpci750/cpci750.c
View File

@ -378,7 +378,6 @@ int misc_init_r ()
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
}
return 0;
}

1
board/esd/hh405/config.mk
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@ -32,4 +32,3 @@ TEXT_BASE = 0xFFF80000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

1
board/esd/hub405/config.mk
View File

@ -29,4 +29,3 @@ TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

60
board/mcc200/mcc200.c
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@ -28,19 +28,12 @@
#include <mpc5xxx.h>
#include <pci.h>
//###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI!
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
//#include "mt48lc16m16a2-75.h"
#include "mt48lc8m32b2-6-7.h"
#endif
extern flash_info_t flash_info[]; /* FLASH chips info */
ulong flash_get_size (ulong base, int banknum);
//###CHD: wenn RAMBOOT gehen wuerde, ....
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
@ -88,7 +81,6 @@ static void sdram_start (int hi_addr)
* is something else than 0x00000000.
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
ulong dramsize = 0;
@ -190,58 +182,6 @@ long int initdram (int board_type)
return dramsize + dramsize2;
}
//###CHD: sowas gibt es bei usn nicht!
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup and enable SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
/* address select register */
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
__asm__ volatile ("sync");
/* find RAM size */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* set SDRAM end address according to size */
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
#else /* CFG_RAMBOOT */
/* Retrieve amount of SDRAM available */
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
#endif /* CFG_RAMBOOT */
return dramsize;
}
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif
int checkboard (void)
{
puts ("Board: MCC200\n");

18
board/mcc200/mt48lc8m32b2-6-7.h
View File

@ -4,27 +4,9 @@
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
//#define SDRAM_MODE 0x00cc0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104
//#define SDRAM_CONFIG1 0xe2329000 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
//#define SDRAM_CONFIG2 0x46e70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
//Christian
//#define SDRAM_MODE 0x00cd0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104
//#define SDRAM_CONFIG1 0xd2322900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
//#define SDRAM_CONFIG2 0x8ad70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
//###CHD: ordentliche Doku dazu! CAS=2, etc.
//STefan
#define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
#define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104
#define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
#define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
#else
#error CONFIG_MPC5200 not defined, please set parameters for your sdram controller in mt48lc8m32b2.h
#endif

1
board/netstar/config.mk
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@ -12,4 +12,3 @@ TEXT_BASE = 0x13FC0000
# Compile the new NAND code
BOARDLIBS = drivers/nand/libnand.a

1
board/netta2/config.mk
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@ -29,4 +29,3 @@ TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
common/cmd_nand.c
View File

@ -442,8 +442,6 @@ void archflashwp(void *archdata, int wp);
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
/*
* Imports from nand_legacy.c
*/

1
doc/README.nand
View File

@ -179,7 +179,6 @@ More Definitions:
#define NAND_MAX_CHIPS 1
NOTE:
=====

2
include/configs/PPChameleonEVB.h
View File

@ -300,8 +300,6 @@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define NAND_WAIT_READY(nand) do { \

5
include/configs/mcc200.h
View File

@ -229,9 +229,8 @@
/*
* GPIO configuration
*/
//###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
//###CHD: 0x10000004 = 32MB SDRAM
//###CHD: 0x90000004 = 64MB SDRAM
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#define CFG_GPS_PORT_CONFIG 0x10000004
/*

1
include/linux/mtd/nand.h
View File

@ -65,7 +65,6 @@ extern void nand_release (struct mtd_info *mtd);
extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
/* This constant declares the max. oobsize / page, which
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.