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armv8/ls1043a: Implement workaround for erratum A009660 

Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Mingkai Hu 2016-02-02 11:28:03 +08:00 committed by York Sun
parent 3e0a0fbbac
commit bbc8e053ba
2 changed files with 20 additions and 0 deletions
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19
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -213,6 +213,24 @@ static void erratum_a009929(void)
#endif
}
/*
* This erratum requires setting a value to eddrtqcr1 to optimal
* the DDR performance. The eddrtqcr1 register is in SCFG space
* of LS1043A and the offset is 0x157_020c.
*/
#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
#error A009660 and A008514 can not be both enabled.
#endif
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
erratum_a009660();
}
#endif

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -178,6 +178,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif