M28EVK: Implement support for new board V2.0
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
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@ -90,6 +90,8 @@ int board_mmc_init(bd_t *bis)
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{
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{
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/* Configure WP as input. */
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/* Configure WP as input. */
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gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
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gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
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/* Turn on the power to the card. */
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gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
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return mxsmmc_initialize(bis, 0, m28_mmc_wp);
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return mxsmmc_initialize(bis, 0, m28_mmc_wp);
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}
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}
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@ -103,10 +105,18 @@ int board_mmc_init(bd_t *bis)
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int fecmxc_mii_postcall(int phy)
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int fecmxc_mii_postcall(int phy)
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{
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{
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#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
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/* KZ8031 PHY on old boards. */
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const uint32_t freq = 0x0080;
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#else
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/* KZ8021 PHY on new boards. */
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const uint32_t freq = 0x0000;
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#endif
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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if (phy == 3)
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if (phy == 3)
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
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return 0;
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return 0;
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}
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}
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@ -123,6 +133,14 @@ int board_eth_init(bd_t *bis)
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CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
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CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
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CLKCTRL_ENET_TIME_SEL_RMII_CLK);
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CLKCTRL_ENET_TIME_SEL_RMII_CLK);
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#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
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/* Reset the new PHY */
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gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
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udelay(10000);
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gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
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udelay(10000);
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#endif
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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if (ret) {
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printf("FEC MXS: Unable to init FEC0\n");
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printf("FEC MXS: Unable to init FEC0\n");
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@ -109,8 +109,9 @@ const iomux_cfg_t iomux_setup[] = {
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */
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MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
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MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */
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MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
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/* GPMI NAND */
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/* GPMI NAND */
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MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
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@ -147,6 +148,9 @@ const iomux_cfg_t iomux_setup[] = {
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MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
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#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
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MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
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#endif
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/* I2C */
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/* I2C */
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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