diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 783c46d882..69afa83562 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -13,7 +13,8 @@
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
- u32 id, ret;
+ u32 id;
+ int ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = id & 0xf;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 581c9d5560..d20953d2ca 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -94,8 +94,9 @@ static void setup_iomux_enet(void)
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -340,39 +341,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
static void disable_lvds(struct display_info_t const *dev)
{
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 0af63d291f..ac001edf3a 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -121,8 +121,9 @@ static void setup_iomux_enet(void)
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
@@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index da0199b168..b54a10b493 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -114,3 +114,18 @@ int gpio_free(unsigned gpio)
{
return 0;
}
+
+int name_to_gpio(const char *name)
+{
+ unsigned bank, pin;
+ char *end;
+
+ bank = simple_strtoul(name, &end, 10);
+
+ if (!*end || *end != ':')
+ return bank;
+
+ pin = simple_strtoul(end + 1, NULL, 10);
+
+ return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
+}
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index d509e30d35..ba57b1a4b9 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver = {
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = ar8021_config,
+ .config = ar8035_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 09a3c52680..0509094555 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev)
#elif defined(CONFIG_MX7)
static int read_cpu_temperature(struct udevice *dev)
{
- unsigned int reg, tmp, start;
+ unsigned int reg, tmp;
unsigned int raw_25c, te1;
int temperature;
unsigned int *priv = dev_get_priv(dev);
@@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev)
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
- start = get_timer(0);
- /* Wait max 100ms */
- do {
- /*
- * Since we can not rely on finish bit, use 1ms delay to get
- * temperature. From RM, 17us is enough to get data, but
- * to gurantee to get the data, delay 100ms here.
- */
+ if (soc_rev() >= CHIP_REV_1_1) {
+ while ((readl(&ccm_anatop->tempsense1) &
+ TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
+ ;
reg = readl(&ccm_anatop->tempsense1);
tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
- } while (get_timer(0) < (start + 100));
+ } else {
+ /*
+ * Since we can not rely on finish bit, use 10ms
+ * delay to get temperature. From RM, 17us is
+ * enough to get data, but to gurantee to get
+ * the data, delay 10ms here.
+ */
+ udelay(10000);
+ reg = readl(&ccm_anatop->tempsense1);
+ tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+ >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
+ }
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 0d775956bf..f9f817596f 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -43,7 +43,7 @@ void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+ clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 2712b27fd1..c946176416 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -241,6 +241,7 @@
#define CONFIG_IMX_THERMAL
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
@@ -257,5 +258,6 @@
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
+#endif
#endif
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index d15a70cedb..f698d4d64e 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -16,3 +16,4 @@ struct watchdog_regs {
#define WCR_WDT 0x08
#define WCR_SRS 0x10
#define SET_WCR_WT(x) (x << 8)
+#define WCR_WT_MSK SET_WCR_WT(0xFF)