ppc4xx: Maintenance patch for VOH405 boards
- add EEPROM write protection - initialize NAND GPIOs - use correct io accessors - slow down I2C clock to 100kHz - enable ext. I2C bus - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
c05569066d
commit
b56bd0fcfc
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@ -22,6 +22,7 @@
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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@ -112,11 +113,11 @@ int misc_init_f (void)
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int misc_init_r (void)
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{
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volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
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volatile unsigned short *lcd_contrast =
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unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
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unsigned short *lcd_contrast =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
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volatile unsigned short *lcd_backlight =
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unsigned short *lcd_backlight =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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@ -180,25 +181,37 @@ int misc_init_r (void)
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/*
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* Reset FPGA via FPGA_INIT pin
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
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udelay(1000); /* wait 1ms */
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out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
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udelay(1000); /* wait 1ms */
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/*
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* Reset external DUARTs
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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udelay(10); /* wait 10us */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
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/*
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* Setup EEPROM write protection
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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*duart0_mcr = 0x08;
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*duart1_mcr = 0x08;
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out_8(duart0_mcr, 0x08);
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out_8(duart1_mcr, 0x08);
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/*
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* Init lcd interface and display logo
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@ -240,17 +253,23 @@ int misc_init_r (void)
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/*
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* Set invert bit in small lcd controller
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*/
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*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
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out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
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in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
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/*
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* Set default contrast voltage on epson vga controller
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*/
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*lcd_contrast = 0x4646;
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out_be16(lcd_contrast, 0x4646);
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/*
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* Enable backlight
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*/
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*lcd_backlight = 0xffff;
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out_be16(lcd_backlight, 0xffff);
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/*
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* Enable external I2C bus
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*/
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
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return (0);
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}
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@ -281,11 +300,6 @@ int checkboard (void)
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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@ -334,3 +348,86 @@ void ide_set_reset(int on)
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}
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}
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#endif /* CONFIG_IDE_RESET */
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#if defined(CONFIG_RESET_PHY_R)
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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#endif
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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if (CFG_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int query = argc == 1;
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int state = 0;
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if (query) {
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/* Query write access state. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
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if (state < 0) {
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puts ("Query of write access state failed.\n");
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} else {
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printf ("Write access for device 0x%0x is %sabled.\n",
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
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state = 0;
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}
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} else {
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if ('0' == argv[1][0]) {
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/* Disable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
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} else {
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/* Enable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
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}
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if (state < 0) {
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puts ("Setup of write access state failed.\n");
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}
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}
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return state;
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}
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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"eepwren - Enable / disable / query EEPROM write access\n",
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NULL);
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#endif /* #if defined(CFG_EEPROM_WREN) */
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@ -52,9 +52,13 @@
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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@ -204,8 +208,6 @@
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#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */
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#define CFG_ATA_BASE_ADDR 0xF0100000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_IDE1_OFFSET 0x0010
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@ -244,11 +246,6 @@
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#if 0 /* test-only */
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#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
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#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
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#endif
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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@ -281,19 +278,12 @@
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
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#if 0 /* test-only */
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/* CAT24WC08/16... */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#else
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#define CFG_EEPROM_WREN 1
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/* CAT24WC32/64... */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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@ -301,7 +291,6 @@
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
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/* 32 byte page write mode using*/
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/* last 5 bits of the address */
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#endif
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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@ -400,18 +389,20 @@
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
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*/
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#define CFG_GPIO0_OSRH 0x40000550
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#define CFG_GPIO0_OSRH 0x00000550
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#define CFG_GPIO0_OSRL 0x00000110
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#define CFG_GPIO0_ISR1H 0x00000000
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#define CFG_GPIO0_ISR1L 0x15555440
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#define CFG_GPIO0_TSRH 0x00000000
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#define CFG_GPIO0_TSRL 0x00000000
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#define CFG_GPIO0_TCR 0xF7FE0017
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#define CFG_GPIO0_TCR 0x777E0017
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#define CFG_DUART_RST (0x80000000 >> 14)
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#define CFG_LCD_ENDIAN (0x80000000 >> 7)
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#define CFG_IIC_ON (0x80000000 >> 8)
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#define CFG_LCD0_RST (0x80000000 >> 30)
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#define CFG_LCD1_RST (0x80000000 >> 31)
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#define CFG_EEPROM_WP (0x80000000 >> 0)
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/*
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* Internal Definitions
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