EXYNOS: Add clock for SPI
Add api to calculate and set the clock for SPI channels Signed-off-by: James Miller <jamesmiller@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Hatim RV
Minkyu Kang
parent
fbb5743308
commit
b56b304252
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@ -25,6 +25,7 @@
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/periph.h>
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/* Epll Clock division values to achive different frequency output */
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static struct set_epll_con_val exynos5_epll_div[] = {
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@ -804,6 +805,122 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
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return 0;
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}
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/**
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* Linearly searches for the most accurate main and fine stage clock scalars
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* (divisors) for a specified target frequency and scalar bit sizes by checking
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* all multiples of main_scalar_bits values. Will always return scalars up to or
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* slower than target.
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*
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* @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
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* @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
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* @param input_freq Clock frequency to be scaled in Hz
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* @param target_freq Desired clock frequency in Hz
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* @param best_fine_scalar Pointer to store the fine stage divisor
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*
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* @return best_main_scalar Main scalar for desired frequency or -1 if none
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* found
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*/
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static int clock_calc_best_scalar(unsigned int main_scaler_bits,
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unsigned int fine_scalar_bits, unsigned int input_rate,
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unsigned int target_rate, unsigned int *best_fine_scalar)
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{
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int i;
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int best_main_scalar = -1;
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unsigned int best_error = target_rate;
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const unsigned int cap = (1 << fine_scalar_bits) - 1;
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const unsigned int loops = 1 << main_scaler_bits;
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debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
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target_rate, cap);
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assert(best_fine_scalar != NULL);
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assert(main_scaler_bits <= fine_scalar_bits);
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*best_fine_scalar = 1;
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if (input_rate == 0 || target_rate == 0)
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return -1;
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if (target_rate >= input_rate)
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return 1;
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for (i = 1; i <= loops; i++) {
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const unsigned int effective_div = max(min(input_rate / i /
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target_rate, cap), 1);
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const unsigned int effective_rate = input_rate / i /
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effective_div;
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const int error = target_rate - effective_rate;
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debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
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effective_rate, error);
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if (error >= 0 && error <= best_error) {
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best_error = error;
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best_main_scalar = i;
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*best_fine_scalar = effective_div;
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}
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}
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return best_main_scalar;
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}
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static int exynos5_set_spi_clk(enum periph_id periph_id,
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unsigned int rate)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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int main;
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unsigned int fine;
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unsigned shift, pre_shift;
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unsigned mask = 0xff;
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u32 *reg;
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main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
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if (main < 0) {
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debug("%s: Cannot set clock rate for periph %d",
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__func__, periph_id);
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return -1;
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}
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main = main - 1;
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fine = fine - 1;
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switch (periph_id) {
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case PERIPH_ID_SPI0:
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reg = &clk->div_peric1;
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shift = 0;
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pre_shift = 8;
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break;
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case PERIPH_ID_SPI1:
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reg = &clk->div_peric1;
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shift = 16;
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pre_shift = 24;
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break;
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case PERIPH_ID_SPI2:
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reg = &clk->div_peric2;
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shift = 0;
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pre_shift = 8;
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break;
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case PERIPH_ID_SPI3:
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reg = &clk->sclk_div_isp;
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shift = 0;
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pre_shift = 4;
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break;
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case PERIPH_ID_SPI4:
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reg = &clk->sclk_div_isp;
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shift = 12;
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pre_shift = 16;
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break;
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default:
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debug("%s: Unsupported peripheral ID %d\n", __func__,
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periph_id);
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return -1;
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}
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clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
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clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
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return 0;
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}
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unsigned long get_pll_clk(int pllreg)
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{
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if (cpu_is_exynos5())
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@ -876,6 +993,14 @@ void set_mipi_clk(void)
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exynos4_set_mipi_clk();
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}
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int set_spi_clk(int periph_id, unsigned int rate)
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{
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if (cpu_is_exynos5())
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return exynos5_set_spi_clk(periph_id, rate);
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else
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return 0;
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}
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int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
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{
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@ -41,5 +41,6 @@ void set_mipi_clk(void);
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void set_i2s_clk_source(void);
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int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
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int set_epll_clk(unsigned long rate);
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int set_spi_clk(int periph_id, unsigned int rate);
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#endif
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