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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

This commit is contained in:
Wolfgang Denk 2008-09-12 15:23:20 +02:00
parent 06c4ab50f5 b18410e508
commit b476b03256
13 changed files with 22 additions and 101 deletions
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4
Makefile
View File

@ -1488,9 +1488,9 @@ v5fx30teval_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
> $(obj)/board/avnet/v5fx30teval/config.tmp
> $(obj)board/avnet/v5fx30teval/config.tmp
@echo "TEXT_BASE := 0xFF1C0000" \
>> $(obj)/board/avnet/v5fx30teval/config.tmp
>> $(obj)board/avnet/v5fx30teval/config.tmp
@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
VOH405_config: unconfig

9
board/amcc/taihu/taihu.c
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@ -78,15 +78,6 @@ int checkboard(void)
return 0;
}
/*************************************************************************
* phys_size_t initdram
*
************************************************************************/
phys_size_t initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}
static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
{
char stat;

1
board/avnet/v5fx30teval/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.tmp

25
board/dave/PPChameleonEVB/PPChameleonEVB.c
View File

@ -203,31 +203,6 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0 /* test-only */
for (;;) {
NAND_DISABLE_CE(1);
udelay(100);
NAND_ENABLE_CE(1);
udelay(100);
}
#endif
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */

31
board/esd/pci405/pci405.c
View File

@ -356,37 +356,6 @@ int checkboard (void)
return 0;
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
#if 0 /* test-only: all PCI405 version must report 16mb */
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
#else
return (16*1024*1024);
#endif
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
int wpeeprom(int wp)
{

5
board/quad100hd/quad100hd.c
View File

@ -86,8 +86,3 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
return CFG_SDRAM_SIZE;
}

1
board/xilinx/ml507/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.tmp

1
board/xilinx/ppc440-generic/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.tmp

2
board/xilinx/ppc440-generic/config.mk
View File

@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
sinclude $(obj)/board/$(BOARDDIR)/config.tmp
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp

23
board/zeus/zeus.c
View File

@ -190,29 +190,6 @@ int checkboard(void)
return (0);
}
static u32 detect_sdram_size(void)
{
u32 val;
u32 size;
mfsdram(mem_mb0cf, val);
size = (4 << 20) << ((val & 0x000e0000) >> 17);
/*
* Check if 2nd bank is enabled too
*/
mfsdram(mem_mb1cf, val);
if (val & 1)
size += (4 << 20) << ((val & 0x000e0000) >> 17);
return size;
}
phys_size_t initdram (int board_type)
{
return detect_sdram_size();
}
static int default_env_var(char *buf, char *var)
{
char *ptr;

14
cpu/ppc4xx/sdram.c
View File

@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
phys_size_t size = mb0cf[i].size;
/*
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
} else {
/*
* We have two identical banks, so the size
* is twice the bank size
*/
size = 2 * size;
}
#endif
/*
* OK, size detected -> all done
*/
return mb0cf[i].size;
return size;
}
}

1
include/configs/quad100hd.h
View File

@ -82,7 +82,6 @@
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1
#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */
/* FIX! SDRAM timings used in datasheet */
#define CFG_SDRAM_CL 3 /* CAS latency */

6
include/configs/zeus.h
View File

@ -309,6 +309,12 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/* ENVIRONMENT VARS */
#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"