ARM: remove broken "m501sk" board
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
Albert ARIBAUD
parent
5bd3814bb7
commit
b1a2bd4bb3
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@ -1,50 +0,0 @@
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := m501sk.o eeprom.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0x21f00000
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@ -1,102 +0,0 @@
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/*
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* Add by Alan Lu, 07-29-2005
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* For ATMEL AT24C16 EEPROM
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#ifdef CONFIG_SYS_EEPROM_AT24C16
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#undef DEBUG
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void eeprom_init(void)
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{
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#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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}
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int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
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unsigned cnt)
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{
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int page, count = 0, i = 0;
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page = offset / 0x100;
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i = offset % 0x100;
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while (count < cnt) {
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if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
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return 1;
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if (i > 0xff) {
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page++;
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i = 0;
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}
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}
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return 0;
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}
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/*
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* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
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* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
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*
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* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
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* 0x00000nxx for EEPROM address selectors and page number at n.
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*/
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int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
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unsigned cnt)
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{
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int page, i = 0, count = 0;
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page = offset / 0x100;
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i = offset % 0x100;
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while (count < cnt) {
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if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
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return 1;
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if (i > 0xff) {
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page++;
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i = 0;
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}
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}
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#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
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udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
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#endif
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return 0;
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}
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#ifndef CONFIG_SPI
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int eeprom_probe(unsigned dev_addr, unsigned offset)
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{
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unsigned char chip;
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/* Probe the chip address */
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#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
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chip = offset >> 8; /* block number */
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#else
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chip = offset >> 16; /* block number */
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#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
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chip |= dev_addr; /* insert device address */
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return (i2c_probe(chip));
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}
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#endif
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#endif
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@ -1,203 +0,0 @@
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/*
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* (C) Copyright 2008
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* Based on modifications by Alan Lu / Artila
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* Author : Timo Tuunainen / Sysart
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Kimmo Leppala / Sysart
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#if defined(CONFIG_DRIVER_ETHER)
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#include <at91rm9200_net.h>
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#include <dm9161.h>
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#endif
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#include "m501sk.h"
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#include "net.h"
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#ifdef CONFIG_M501SK
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void m501sk_gpio_init(void)
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{
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AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
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1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
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1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
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AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
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1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
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1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
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AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
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AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
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AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
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AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
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AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
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/* Power OFF all USART's LEDs */
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AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
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AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
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AT91C_PA23_TXD2;
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AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
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AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
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AT91C_PA23_TXD2;
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AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
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AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
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AT91C_PA23_TXD2;
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AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
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AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
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AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
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}
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uchar m501sk_gpio_set(M501SK_PIO io)
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{
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uchar status = 0xff;
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switch (io) {
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case M501SK_DEBUG_LED1:
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case M501SK_DEBUG_LED2:
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case M501SK_DEBUG_LED3:
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case M501SK_DEBUG_LED4:
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case M501SK_READY_LED:
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AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
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status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
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break;
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case M501SK_BUZZER:
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AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
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status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
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break;
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}
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return status;
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}
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uchar m501sk_gpio_clear(M501SK_PIO io)
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{
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uchar status = 0xff;
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switch (io) {
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case M501SK_DEBUG_LED1:
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case M501SK_DEBUG_LED2:
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case M501SK_DEBUG_LED3:
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case M501SK_DEBUG_LED4:
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case M501SK_READY_LED:
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AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
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status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
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break;
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case M501SK_BUZZER:
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AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
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status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
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break;
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}
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return status;
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}
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/*
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* Miscelaneous platform dependent initialisations
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*/
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* Correct IRDA resistor problem */
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/* Set PA23_TXD in Output */
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((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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gd->bd->bi_arch_number = MACH_TYPE_M501;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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m501sk_gpio_init();
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/* Do interrupt init here, because flash needs timers */
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timer_init();
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flash_init();
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return 0;
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}
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int dram_init(void)
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{
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int i = 0;
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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for (i = 0; i < 500; i++) {
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m501sk_gpio_clear(M501SK_DEBUG_LED3);
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m501sk_gpio_clear(M501SK_BUZZER);
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udelay(250);
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m501sk_gpio_set(M501SK_DEBUG_LED3);
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m501sk_gpio_set(M501SK_BUZZER);
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udelay(80);
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}
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m501sk_gpio_clear(M501SK_BUZZER);
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m501sk_gpio_clear(M501SK_DEBUG_LED3);
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return 0;
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}
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int board_late_init(void)
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{
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#if defined(CONFIG_CMD_NET)
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eth_init(gd->bd);
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eth_halt();
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#endif
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/* Protect U-Boot, kernel & ramdisk memory addresses */
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run_command("protect on 10000000 1041ffff", 0);
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return 0;
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}
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#ifdef CONFIG_DRIVER_ETHER
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#if defined(CONFIG_CMD_NET)
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/*
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* Name:
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* at91rm9200_GetPhyInterface
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* Description:
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* Initialise the interface functions to the PHY
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* Arguments:
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* None
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* Return value:
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* None
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*/
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void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
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{
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p_phyops->Init = dm9161_InitPhy;
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p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
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p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
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p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* CONFIG_DRIVER_ETHER */
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#ifdef CONFIG_DRIVER_AT91EMAC
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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rc = at91emac_register(bis, 0);
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return rc;
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}
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#endif
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#endif /* CONFIG_M501SK */
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@ -1,167 +0,0 @@
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/*
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* linux/include/asm/arch-at91/hardware.h
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*
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* Copyright (C) 2003 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __M501SK_H
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#define __M501SK_H
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#ifndef __ASSEMBLY__
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#include <asm/arch-at91rm9200/AT91RM9200.h>
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#else
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#include <asm/arch-at91rm9200/AT91RM9200_inc.h>
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#endif
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#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
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#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */
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#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 TxD */
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#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */
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/* ========== Register definition for PIOD peripheral ========== */
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#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */
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#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */
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#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */
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#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */
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#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */
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#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */
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#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */
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#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */
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#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */
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#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */
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#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */
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#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */
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#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */
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#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */
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#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */
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#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */
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#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */
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#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */
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#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */
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#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */
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#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */
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#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */
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#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */
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#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */
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#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */
|
||||
#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */
|
||||
#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */
|
||||
#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */
|
||||
#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */
|
||||
|
||||
#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */
|
||||
#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Enet MAC Tx Data 0*/
|
||||
#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */
|
||||
#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Enet MAC Tx Data 1*/
|
||||
#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
|
||||
#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/
|
||||
#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */
|
||||
#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
|
||||
#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */
|
||||
#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */
|
||||
#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
|
||||
#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */
|
||||
#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */
|
||||
#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
|
||||
#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */
|
||||
#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */
|
||||
#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
|
||||
#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */
|
||||
#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */
|
||||
#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
|
||||
#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */
|
||||
#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */
|
||||
#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
|
||||
#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */
|
||||
#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */
|
||||
#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
|
||||
#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */
|
||||
#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */
|
||||
#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
|
||||
#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Perip CS 1 */
|
||||
#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */
|
||||
#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
|
||||
#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Perip CS 2 */
|
||||
#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */
|
||||
#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */
|
||||
#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC TxD 2 */
|
||||
#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
|
||||
#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */
|
||||
#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */
|
||||
#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
|
||||
#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */
|
||||
#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */
|
||||
#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
|
||||
#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 RTS */
|
||||
#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */
|
||||
#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
|
||||
#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */
|
||||
#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */
|
||||
#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
|
||||
#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 RTS */
|
||||
#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */
|
||||
#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
|
||||
#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */
|
||||
#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */
|
||||
#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
|
||||
#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */
|
||||
#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
|
||||
#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */
|
||||
#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */
|
||||
#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Enet MAC TxD 3 */
|
||||
#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */
|
||||
#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */
|
||||
#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */
|
||||
#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Enet MAC TxCE */
|
||||
#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */
|
||||
#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */
|
||||
#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */
|
||||
#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/
|
||||
#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */
|
||||
#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */
|
||||
#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/
|
||||
#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */
|
||||
#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */
|
||||
#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */
|
||||
#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */
|
||||
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
|
||||
#define AT91C_PIO_PC5 ((unsigned int) 1 << 5)
|
||||
#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */
|
||||
#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */
|
||||
#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */
|
||||
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */
|
||||
#define AT91C_PIO_PB8 ((unsigned int) 1 << 8)
|
||||
#define AT91C_PIO_PB9 ((unsigned int) 1 << 9)
|
||||
#define AT91C_PIO_PB10 ((unsigned int) 1 << 10)
|
||||
#define AT91C_PIO_PB11 ((unsigned int) 1 << 11)
|
||||
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17)
|
||||
#define AT91C_PIO_PB28 ((unsigned int) 1 << 28)
|
||||
#define AT91C_PIO_PB29 ((unsigned int) 1 << 29)
|
||||
|
||||
typedef enum {
|
||||
M501SK_BUZZER = 38,
|
||||
M501SK_DEBUG_LED1 = 96,
|
||||
M501SK_DEBUG_LED2,
|
||||
M501SK_DEBUG_LED3,
|
||||
M501SK_DEBUG_LED4,
|
||||
M501SK_READY_LED = 102,
|
||||
} M501SK_PIO;
|
||||
|
||||
void m501sk_gpio_init(void);
|
||||
uchar m501sk_gpio_set(M501SK_PIO io);
|
||||
uchar m501sk_gpio_clear(M501SK_PIO io);
|
||||
|
||||
#endif
|
||||
|
|
@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel
|
|||
eb_cpux9k2 arm arm920t - BuS at91
|
||||
cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
|
||||
cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
|
||||
m501sk arm arm920t - - at91rm9200
|
||||
at91rm9200dk arm arm920t - atmel at91rm9200
|
||||
mx1ads arm arm920t - - imx
|
||||
scb9328 arm arm920t - - imx
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU removed Commit last known maintainer/contact
|
||||
=============================================================================
|
||||
m501sk arm arm920t - 2011-07-17
|
||||
kb9202 arm arm920t - 2011-07-17
|
||||
csb637 arm arm920t - 2011-07-17
|
||||
cmc_pu2 arm arm920t - 2011-07-17
|
||||
|
|
|
|||
|
|
@ -1,228 +0,0 @@
|
|||
/*
|
||||
* Based on Modifications by Alan Lu / Artila and
|
||||
* Rick Bronson <rick@efn.org>
|
||||
*
|
||||
* Configuration settings for the Artila M-501 starter kit,
|
||||
* with V02 processor card.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_AT91_LEGACY
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
/* from 18.432 MHz crystal (18432000 / 4 * 39) */
|
||||
#define AT91C_MAIN_CLOCK 179712000
|
||||
/* Perip clock (AT91C_MASTER_CLOCK / 3) */
|
||||
#define AT91C_MASTER_CLOCK 59904000
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
|
||||
#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_MENUPROMPT "."
|
||||
/*
|
||||
* LowLevel Init
|
||||
*/
|
||||
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
|
||||
/* flash */
|
||||
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
|
||||
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
|
||||
|
||||
/* clocks */
|
||||
#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
|
||||
#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
|
||||
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
|
||||
#define CONFIG_SYS_MCKR_VAL 0x00000202
|
||||
|
||||
/* sdram */
|
||||
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
|
||||
#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
|
||||
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
|
||||
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
|
||||
#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_AT24C16
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
|
||||
#undef CONFIG_RTC_DS1338
|
||||
#define CONFIG_RTC_RS5C372A
|
||||
#undef CONFIG_POST
|
||||
#define CONFIG_M501SK
|
||||
#define CONFIG_CMC_PU2
|
||||
|
||||
/* define one of these to choose the DBGU, USART0 or USART1 as console */
|
||||
#define CONFIG_AT91RM9200_USART
|
||||
#define CONFIG_DBGU
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
|
||||
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
|
||||
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
|
||||
|
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
|
||||
"initrd=0x20800000,8192000 ramdisk_size=15360 " \
|
||||
"root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
|
||||
"128k(loader)ro,128k(reserved)ro,1408k(linux)" \
|
||||
"ro,2560k(ramdisk)ro,-(userdisk)"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_IPADDR 192.168.1.100
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.254
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"unlock=yes\0"
|
||||
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#undef CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_POST
|
||||
#define CONFIG_CMD_MISC
|
||||
#define CONFIG_CMD_LOADS
|
||||
#define CONFIG_CMD_IMI
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
|
||||
/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00100000
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#ifdef CONFIG_NET_MULTI
|
||||
#define CONFIG_DRIVER_AT91EMAC 1
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
#else
|
||||
#define CONFIG_DRIVER_ETHER 1
|
||||
#endif
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_AT91C_USE_RMII
|
||||
|
||||
#define PHYS_FLASH_1 0x10000000
|
||||
#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_DATAFLASH
|
||||
#define CONFIG_ENV_OFFSET 0x20000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
|
||||
#define CONFIG_ENV_SIZE 2048
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_OFFSET 1024
|
||||
#define CONFIG_ENV_SIZE 1024
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
|
||||
|
||||
/* use for protect flash sectors */
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2
|
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue