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ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_* 

The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook.  Follow this abbreviation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2015-12-16 10:42:29 +09:00
parent a1c4bf8666
commit b04ed73a50
2 changed files with 4 additions and 4 deletions
arch/arm/mach-uniphier
ddrphy
ddrphy-training.c
include/mach
ddrphy-regs.h

4
arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
View File

@ -32,8 +32,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
/* Use Multi-Purpose Register for DQS gate training */
tmp |= DTCR_DTMPR;
/* Specify the rank enabled for data-training */
tmp &= ~DTCR_RNKEN_MASK;
tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
tmp &= ~DTCR_RANKEN_MASK;
tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
writel(tmp, p);
}

4
arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
View File

@ -147,8 +147,8 @@ struct ddrphy {
#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))