Exynos542x: CPU: Power down all secondary cores
This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel. Secondary core power down happens in following steps: Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Akshay Saraswat
Minkyu Kang
parent
1a8aae9b94
commit
ac0d98cd55
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@ -700,6 +700,9 @@
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#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
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#else
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#define CPU_CONFIG_STATUS_OFFSET 0x80
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#define CPU_RST_FLAG_VAL 0xFCBA0D10
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#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
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/* APLL_CON1 */
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@ -31,7 +31,9 @@
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#include <asm/arch/tzpc.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/system.h>
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#include "common_setup.h"
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#include "exynos5_setup.h"
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/* These are the things we can do during low-level init */
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enum {
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@ -42,6 +44,68 @@ enum {
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DO_POWER = 1 << 4,
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};
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#ifdef CONFIG_EXYNOS5420
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/*
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* Pointer to this function is stored in iRam which is used
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* for jump and power down of a specific core.
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*/
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static void power_down_core(void)
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{
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uint32_t tmp, core_id, core_config;
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/* Get the unique core id */
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/*
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* Multiprocessor Affinity Register
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* [11:8] Cluster ID
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* [1:0] CPU ID
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*/
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mrc_mpafr(core_id);
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tmp = core_id & 0x3;
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core_id = (core_id >> 6) & ~3;
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core_id |= tmp;
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core_id &= 0x3f;
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/* Set the status of the core to low */
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core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
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core_config += EXYNOS5420_CPU_CONFIG_BASE;
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writel(0x0, core_config);
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/* Core enter WFI */
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wfi();
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}
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/*
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* Configurations for secondary cores are inapt at this stage.
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* Reconfigure secondary cores. Shutdown and change the status
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* of all cores except the primary core.
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*/
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static void secondary_cores_configure(void)
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{
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uint32_t core_id;
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/* Store jump address for power down of secondary cores */
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writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
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/* Need all core power down check */
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dsb();
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sev();
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/*
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* Power down all cores(secondary) while primary core must
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* wait for all cores to go down.
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*/
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for (core_id = 1; core_id != CONFIG_CORE_COUNT; core_id++) {
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while ((readl(EXYNOS5420_CPU_STATUS_BASE
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+ (core_id * CPU_CONFIG_STATUS_OFFSET))
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& 0xff) != 0x0) {
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isb();
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sev();
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}
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isb();
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}
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}
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#endif
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int do_lowlevel_init(void)
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{
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uint32_t reset_status;
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@ -49,6 +113,11 @@ int do_lowlevel_init(void)
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arch_cpu_init();
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#ifdef CONFIG_EXYNOS5420
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/* Reconfigure secondary cores */
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secondary_cores_configure();
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#endif
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reset_status = get_reset_status();
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switch (reset_status) {
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@ -153,6 +153,10 @@
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#define EXYNOS5420_CLOCK_BASE 0x10010000
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#define EXYNOS5420_POWER_BASE 0x10040000
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#define EXYNOS5420_SWRESET 0x10040400
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#define EXYNOS5420_INFORM_BASE 0x10040800
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#define EXYNOS5420_SPARE_BASE 0x10040900
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#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
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#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
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#define EXYNOS5420_SYSREG_BASE 0x10050000
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#define EXYNOS5420_TZPC_BASE 0x100E0000
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#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
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@ -186,6 +190,7 @@
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#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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/* CPU detection macros */
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@ -37,6 +37,93 @@ struct exynos5_sysreg {
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#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
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#ifdef CONFIG_EXYNOS5420
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/*
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* Data Synchronization Barrier acts as a special kind of memory barrier.
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* No instruction in program order after this instruction executes until
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* this instruction completes. This instruction completes when:
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* - All explicit memory accesses before this instruction complete.
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* - All Cache, Branch predictor and TLB maintenance operations before
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* this instruction complete.
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*/
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#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
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/*
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* This instruction causes an event to be signaled to all cores
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* within a multiprocessor system. If SEV is implemented,
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* WFE must also be implemented.
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*/
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#define sev() __asm__ __volatile__ ("sev\n\t" : : );
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/*
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* If the Event Register is not set, WFE suspends execution until
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* one of the following events occurs:
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* - an IRQ interrupt, unless masked by the CPSR I-bit
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* - an FIQ interrupt, unless masked by the CPSR F-bit
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* - an Imprecise Data abort, unless masked by the CPSR A-bit
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* - a Debug Entry request, if Debug is enabled
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* - an Event signaled by another processor using the SEV instruction.
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* If the Event Register is set, WFE clears it and returns immediately.
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* If WFE is implemented, SEV must also be implemented.
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*/
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#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
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/* Move 0xd3 value to CPSR register to enable SVC mode */
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#define svc32_mode_en() __asm__ __volatile__ \
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("@ I&F disable, Mode: 0x13 - SVC\n\t" \
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"msr cpsr_c, #0x13|0xC0\n\t" : : )
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/* Set program counter with the given value */
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#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
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/* Read Main Id register */
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#define mrc_midr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
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/* Read Multiprocessor Affinity Register */
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#define mrc_mpafr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
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/* Read System Control Register */
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#define mrc_sctlr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
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/* Read Auxiliary Control Register */
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#define mrc_auxr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
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/* Read L2 Control register */
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#define mrc_l2_ctlr(x) __asm__ __volatile__ \
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("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
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/* Read L2 Auxilliary Control register */
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#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
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("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
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/* Write System Control Register */
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#define mcr_sctlr(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
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/* Write Auxiliary Control Register */
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#define mcr_auxr(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
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/* Invalidate all instruction caches to PoU */
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#define mcr_icache(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
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/* Invalidate unified TLB */
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#define mcr_tlb(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
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/* Write L2 Control register */
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#define mcr_l2_ctlr(x) __asm__ __volatile__ \
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("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
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/* Write L2 Auxilliary Control register */
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#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
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("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
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#endif
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void set_usbhost_mode(unsigned int mode);
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void set_system_display_ctrl(void);
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int exynos_lcd_early_init(const void *blob);
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