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net: sun8i_emac: Drop redundant and incorrect setting of syscon register 

In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.

It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.

This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.

Fixes: a29710c525 ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Chen-Yu Tsai 2016-07-22 18:16:10 +08:00 committed by Hans de Goede
parent 687284483c
commit a85ba87dbe
1 changed files with 1 additions and 9 deletions
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10
drivers/net/sun8i_emac.c
View File

@ -22,10 +22,6 @@
#include <miiphy.h>
#include <net.h>
#define SCTL_EMAC_TX_CLK_SRC_MII BIT(0)
#define SCTL_EMAC_EPIT_MII BIT(2)
#define SCTL_EMAC_CLK_SEL BIT(18) /* 25 Mhz */
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
@ -589,9 +585,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* Set clock gating for ephy */
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
/* Set Tx clock source as MII with rate 25 MZ */
setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
/* Deassert EPHY */
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
}
@ -693,12 +686,11 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
priv->mac_reg = (void *)pdata->iobase;
sun8i_emac_board_setup(priv);
sun8i_emac_set_syscon(priv);
sun8i_mdio_init(dev->name, priv);
priv->bus = miiphy_get_dev_by_name(dev->name);
sun8i_emac_set_syscon(priv);
return sun8i_phy_init(priv, dev);
}