Merge branch 'master' of git://git.denx.de/u-boot-mpc86xx
This commit is contained in:
Wolfgang Denk
commit
a7faab9d11
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@ -36,10 +36,6 @@
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#include "../common/pixis.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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void sdram_init(void);
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long int fixed_sdram(void);
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void mpc8610hpcd_diu_init(void);
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@ -134,13 +130,6 @@ initdram(int board_type)
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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@ -55,9 +55,6 @@ struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
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SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
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#if !defined(CONFIG_SPD_EEPROM)
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
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#endif
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
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};
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@ -33,10 +33,6 @@
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#include "../common/pixis.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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long int fixed_sdram(void);
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int board_early_init_f(void)
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@ -70,13 +66,6 @@ initdram(int board_type)
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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@ -38,10 +38,6 @@
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#include <libfdt.h>
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#include <fdt_support.h>
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc (unsigned int dram_size);
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#endif
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long int fixed_sdram (void);
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int board_early_init_f (void)
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@ -71,13 +67,6 @@ phys_size_t initdram (int board_type)
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc (dram_size);
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#endif
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puts (" DDR: ");
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return dram_size;
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}
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@ -202,8 +202,12 @@ boot_warm:
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mtmsr 0
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#endif
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/* Invalidate BATs */
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bl invalidate_bats
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sync
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/* Invalidate all of TLB before MMU turn on */
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bl clear_tlbs
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sync
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#ifdef CONFIG_SYS_L2
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/* init the L2 cache */
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@ -275,7 +279,6 @@ in_flash:
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/* setup the rest of the bats */
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bl setup_bats
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bl clear_tlbs
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sync
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#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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@ -617,7 +620,6 @@ relocate_code:
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mr r1, r3 /* Set new stack pointer */
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mr r9, r4 /* Save copy of Global Data pointer */
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mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
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mr r10, r5 /* Save copy of Destination Address */
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mr r3, r5 /* Destination Address */
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@ -644,16 +646,6 @@ relocate_code:
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/*
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* Now relocate code
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*/
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#ifdef CONFIG_ECC
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bl board_relocate_rom
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sync
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mr r3, r10 /* Destination Address */
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lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
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ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
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lwz r5, GOT(__init_end)
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sub r5, r5, r4
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li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
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#else
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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@ -675,7 +667,6 @@ relocate_code:
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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#endif
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/*
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* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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@ -708,9 +699,6 @@ relocate_code:
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blr
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in_ram:
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#ifdef CONFIG_ECC
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bl board_init_ecc
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#endif
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/*
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* Relocation Function, r14 point to got2+0x8000
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*
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@ -126,15 +126,6 @@
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#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
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#define CONFIG_SYS_DDR_SBE 0x000f0000
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/*
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* FIXME: Not used in fixed_sdram function
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*/
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#define CONFIG_SYS_DDR_MODE 0x00000022
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
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#endif
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@ -139,17 +139,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
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#define CONFIG_SYS_DDR_CONTROL2 0x04400000
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/*
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* FIXME: Not used in fixed_sdram function
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*/
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#define CONFIG_SYS_DDR_MODE 0x00000022
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
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#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_ID_EEPROM
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