MIPS: use asm.h macros in mips32 start.S
Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton
Daniel Schwierzeck
parent
d4d774e00e
commit
a39b1cb7f0
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@ -8,6 +8,7 @@
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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@ -98,8 +99,8 @@ _start:
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reset:
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/* Clear watch registers */
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mtc0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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MTC0 zero, CP0_WATCHLO
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MTC0 zero, CP0_WATCHHI
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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@ -116,21 +117,26 @@ reset:
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mtc0 t0, CP0_CONFIG
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#endif
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/* Initialize $gp */
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/*
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* Initialize $gp, force pointer sized alignment of bal instruction to
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* forbid the compiler to put nop's between bal and _gp. This is
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* required to keep _gp and ra aligned to 8 byte.
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*/
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.align PTRLOG
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bal 1f
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nop
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.word _gp
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PTR _gp
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1:
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lw gp, 0(ra)
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PTR_L gp, 0(ra)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* Initialize any external memory */
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la t9, lowlevel_init
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PTR_LA t9, lowlevel_init
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jalr t9
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nop
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/* Initialize caches... */
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la t9, mips_cache_reset
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PTR_LA t9, mips_cache_reset
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jalr t9
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nop
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@ -140,15 +146,15 @@ reset:
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#endif
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/* Set up temporary stack */
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li t0, -16
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li t1, CONFIG_SYS_INIT_SP_ADDR
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PTR_LI t0, -16
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PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
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and sp, t1, t0 # force 16 byte alignment
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sub sp, sp, GD_SIZE # reserve space for gd
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PTR_SUB sp, sp, GD_SIZE # reserve space for gd
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and sp, sp, t0 # force 16 byte alignment
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move k0, sp # save gd pointer
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#ifdef CONFIG_SYS_MALLOC_F_LEN
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li t2, CONFIG_SYS_MALLOC_F_LEN
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sub sp, sp, t2 # reserve space for early malloc
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PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN
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PTR_SUB sp, sp, t2 # reserve space for early malloc
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and sp, sp, t0 # force 16 byte alignment
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#endif
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move fp, sp
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@ -158,14 +164,14 @@ reset:
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1:
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sw zero, 0(t0)
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blt t0, t1, 1b
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addi t0, 4
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PTR_ADDI t0, 4
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#ifdef CONFIG_SYS_MALLOC_F_LEN
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addu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
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PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
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sw sp, 0(t0)
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#endif
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la t9, board_init_f
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PTR_LA t9, board_init_f
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jr t9
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move ra, zero
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@ -188,14 +194,14 @@ relocate_code:
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move s0, a1 # save gd in s0
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move s2, a2 # save destination address in s2
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li t0, CONFIG_SYS_MONITOR_BASE
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sub s1, s2, t0 # s1 <-- relocation offset
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PTR_LI t0, CONFIG_SYS_MONITOR_BASE
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PTR_SUB s1, s2, t0 # s1 <-- relocation offset
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la t3, in_ram
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lw t2, -12(t3) # t2 <-- __image_copy_end
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PTR_LA t3, in_ram
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PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
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move t1, a2
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add gp, s1 # adjust gp
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PTR_ADD gp, s1 # adjust gp
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/*
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* t0 = source address
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@ -205,26 +211,26 @@ relocate_code:
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1:
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lw t3, 0(t0)
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sw t3, 0(t1)
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addu t0, 4
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PTR_ADDU t0, 4
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blt t0, t2, 1b
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addu t1, 4
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PTR_ADDU t1, 4
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/* If caches were enabled, we would have to flush them here. */
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sub a1, t1, s2 # a1 <-- size
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la t9, flush_cache
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PTR_SUB a1, t1, s2 # a1 <-- size
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PTR_LA t9, flush_cache
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jalr t9
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move a0, s2 # a0 <-- destination address
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/* Jump to where we've relocated ourselves */
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addi t0, s2, in_ram - _start
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PTR_ADDI t0, s2, in_ram - _start
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jr t0
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nop
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.word __rel_dyn_end
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.word __rel_dyn_start
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.word __image_copy_end
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.word _GLOBAL_OFFSET_TABLE_
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.word num_got_entries
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PTR __rel_dyn_end
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PTR __rel_dyn_start
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PTR __image_copy_end
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PTR _GLOBAL_OFFSET_TABLE_
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PTR num_got_entries
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in_ram:
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/*
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@ -233,46 +239,46 @@ in_ram:
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* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
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* generated by GNU ld. Skip these reserved entries from relocation.
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*/
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lw t3, -4(t0) # t3 <-- num_got_entries
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lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
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add t8, s1 # t8 now holds relocated _G_O_T_
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addi t8, t8, 8 # skipping first two entries
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li t2, 2
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PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
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PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
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PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
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PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries
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PTR_LI t2, 2
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1:
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lw t1, 0(t8)
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PTR_L t1, 0(t8)
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beqz t1, 2f
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add t1, s1
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sw t1, 0(t8)
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PTR_ADD t1, s1
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PTR_S t1, 0(t8)
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2:
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addi t2, 1
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PTR_ADDI t2, 1
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blt t2, t3, 1b
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addi t8, 4
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PTR_ADDI t8, PTRSIZE
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/* Update dynamic relocations */
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lw t1, -16(t0) # t1 <-- __rel_dyn_start
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lw t2, -20(t0) # t2 <-- __rel_dyn_end
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PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
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PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
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b 2f # skip first reserved entry
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addi t1, 8
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PTR_ADDI t1, 2 * PTRSIZE
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1:
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lw t8, -4(t1) # t8 <-- relocation info
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li t3, 3
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PTR_LI t3, 3
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bne t8, t3, 2f # skip non R_MIPS_REL32 entries
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nop
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lw t3, -8(t1) # t3 <-- location to fix up in FLASH
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PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
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lw t8, 0(t3) # t8 <-- original pointer
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add t8, s1 # t8 <-- adjusted pointer
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PTR_L t8, 0(t3) # t8 <-- original pointer
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PTR_ADD t8, s1 # t8 <-- adjusted pointer
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add t3, s1 # t3 <-- location to fix up in RAM
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sw t8, 0(t3)
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PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
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PTR_S t8, 0(t3)
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2:
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blt t1, t2, 1b
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addi t1, 8 # each rel.dyn entry is 8 bytes
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PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
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/*
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* Clear BSS
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@ -280,17 +286,17 @@ in_ram:
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* GOT is now relocated. Thus __bss_start and __bss_end can be
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* accessed directly via $gp.
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*/
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la t1, __bss_start # t1 <-- __bss_start
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la t2, __bss_end # t2 <-- __bss_end
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PTR_LA t1, __bss_start # t1 <-- __bss_start
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PTR_LA t2, __bss_end # t2 <-- __bss_end
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1:
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sw zero, 0(t1)
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PTR_S zero, 0(t1)
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blt t1, t2, 1b
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addi t1, 4
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PTR_ADDI t1, PTRSIZE
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move a0, s0 # a0 <-- gd
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move a1, s2
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la t9, board_init_r
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PTR_LA t9, board_init_r
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jr t9
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move ra, zero
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