powerpc: mpc5xxx: PM520 board support
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Josef Wagner <Wagner@Microsys.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
ad734f7dc2
commit
a258e732a7
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@ -44,9 +44,6 @@ config TARGET_MOTIONPRO
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config TARGET_MUNICES
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config TARGET_MUNICES
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bool "Support munices"
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bool "Support munices"
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config TARGET_PM520
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bool "Support PM520"
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config TARGET_V38B
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config TARGET_V38B
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bool "Support v38b"
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bool "Support v38b"
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@ -115,7 +112,6 @@ source "board/jupiter/Kconfig"
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source "board/motionpro/Kconfig"
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source "board/motionpro/Kconfig"
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source "board/munices/Kconfig"
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source "board/munices/Kconfig"
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source "board/phytec/pcm030/Kconfig"
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source "board/phytec/pcm030/Kconfig"
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source "board/pm520/Kconfig"
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source "board/tqc/tqm5200/Kconfig"
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source "board/tqc/tqm5200/Kconfig"
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source "board/v38b/Kconfig"
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source "board/v38b/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_PM520
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config SYS_BOARD
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default "pm520"
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config SYS_CONFIG_NAME
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default "PM520"
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endif
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@ -1,9 +0,0 @@
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PM520 BOARD
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M: Josef Wagner <Wagner@Microsys.de>
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S: Maintained
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F: board/pm520/
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F: include/configs/PM520.h
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F: configs/PM520_defconfig
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F: configs/PM520_DDR_defconfig
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F: configs/PM520_ROMBOOT_defconfig
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F: configs/PM520_ROMBOOT_DDR_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := pm520.o flash.o
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@ -1,659 +0,0 @@
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/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/byteorder/swab.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Board support for 1 or 2 flash devices */
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#define FLASH_PORT_WIDTH32
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#undef FLASH_PORT_WIDTH16
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#ifdef FLASH_PORT_WIDTH16
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#define FLASH_PORT_WIDTH ushort
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#define FLASH_PORT_WIDTHV vu_short
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#define SWAP(x) (x)
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#else
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#define FLASH_PORT_WIDTH ulong
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#define FLASH_PORT_WIDTHV vu_long
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#define SWAP(x) (x)
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#endif
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/* Intel-compatible flash ID */
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#define INTEL_COMPAT 0x00890089
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#define INTEL_ALT 0x00B000B0
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/* Intel-compatible flash commands */
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#define INTEL_PROGRAM 0x00100010
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#define INTEL_ERASE 0x00200020
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#define INTEL_CLEAR 0x00500050
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#define INTEL_LOCKBIT 0x00600060
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#define INTEL_PROTECT 0x00010001
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#define INTEL_STATUS 0x00700070
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#define INTEL_READID 0x00900090
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#define INTEL_CONFIRM 0x00D000D0
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#define INTEL_RESET 0xFFFFFFFF
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/* Intel-compatible flash status bits */
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#define INTEL_FINISHED 0x00800080
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#define INTEL_OK 0x00800080
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (FPW *addr, flash_info_t *info);
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static int write_data (flash_info_t *info, ulong dest, FPW data);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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void inline spin_wheel (void);
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static void flash_sync_real_protect (flash_info_t * info);
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static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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int i;
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ulong size = 0;
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extern void flash_preinit(void);
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extern void flash_afterinit(ulong, ulong);
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ulong flashbase = CONFIG_SYS_FLASH_BASE;
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flash_preinit();
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
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switch (i) {
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case 0:
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memset(&flash_info[i], 0, sizeof(flash_info_t));
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flash_get_size ((FPW *) flashbase, &flash_info[i]);
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flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
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break;
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default:
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panic ("configured to many flash banks!\n");
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break;
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}
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size += flash_info[i].size;
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/* get the h/w and s/w protection status in sync */
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flash_sync_real_protect(&flash_info[i]);
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}
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/* Protect monitor and environment sectors
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*/
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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#ifndef CONFIG_BOOT_ROM
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flash_protect ( FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[0] );
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#endif
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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flash_protect ( FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
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#endif
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flash_afterinit(flash_info[0].start[0], flash_info[0].size);
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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return;
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL:
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printf ("INTEL ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F256J3A:
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printf ("28F256J3A\n");
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break;
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case FLASH_28F128J3A:
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printf ("28F128J3A\n");
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break;
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case FLASH_28F640J3A:
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printf ("28F640J3A\n");
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break;
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case FLASH_28F320J3A:
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printf ("28F320J3A\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (FPW *addr, flash_info_t *info)
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{
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volatile FPW value;
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/* Write auto select command: read Manufacturer ID */
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addr[0x5555] = (FPW) 0x00AA00AA;
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addr[0x2AAA] = (FPW) 0x00550055;
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addr[0x5555] = (FPW) 0x00900090;
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mb ();
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udelay(100);
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value = addr[0];
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switch (value) {
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case (FPW) INTEL_MANUFACT:
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (0); /* no or unknown flash */
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}
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mb ();
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value = addr[1]; /* device ID */
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switch (value) {
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case (FPW) INTEL_ID_28F256J3A:
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info->flash_id += FLASH_28F256J3A;
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/* In U-Boot we support only 32 MB (no bank-switching) */
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info->sector_count = 256 / 2;
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info->size = 0x04000000 / 2;
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info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
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break; /* => 32 MB */
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case (FPW) INTEL_ID_28F128J3A:
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info->flash_id += FLASH_28F128J3A;
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info->sector_count = 128;
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info->size = 0x02000000;
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info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
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break; /* => 32 MB */
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case (FPW) INTEL_ID_28F640J3A:
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info->flash_id += FLASH_28F640J3A;
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info->sector_count = 64;
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info->size = 0x01000000;
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info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
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break; /* => 16 MB */
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case (FPW) INTEL_ID_28F320J3A:
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info->flash_id += FLASH_28F320J3A;
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info->sector_count = 32;
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info->size = 0x800000;
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info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
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break; /* => 8 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
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printf ("** ERROR: sector count %d > max (%d) **\n",
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info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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}
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (info->size);
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}
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/*
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* This function gets the u-boot flash sector protection status
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* (flash_info_t.protect[]) in sync with the sector protection
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* status stored in hardware.
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*/
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static void flash_sync_real_protect (flash_info_t * info)
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{
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int i;
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F256J3A:
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case FLASH_28F128J3A:
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case FLASH_28F640J3A:
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case FLASH_28F320J3A:
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for (i = 0; i < info->sector_count; ++i) {
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info->protect[i] = intel_sector_protected(info, i);
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}
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break;
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default:
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/* no h/w protect support */
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break;
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}
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}
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/*
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* checks if "sector" in bank "info" is protected. Should work on intel
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* strata flash chips 28FxxxJ3x in 8-bit mode.
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* Returns 1 if sector is protected (or timed-out while trying to read
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* protection status), 0 if it is not.
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*/
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static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
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{
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FPWV *addr;
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FPWV *lock_conf_addr;
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ulong start;
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unsigned char ret;
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/*
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* first, wait for the WSM to be finished. The rationale for
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* waiting for the WSM to become idle for at most
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* CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
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* because of: (1) erase, (2) program or (3) lock bit
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* configuration. So we just wait for the longest timeout of
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* the (1)-(3), i.e. the erase timeout.
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*/
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/* wait at least 35ns (W12) before issuing Read Status Register */
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udelay(1);
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addr = (FPWV *) info->start[sector];
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*addr = (FPW) INTEL_STATUS;
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start = get_timer (0);
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while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
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if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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*addr = (FPW) INTEL_RESET; /* restore read mode */
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printf("WSM busy too long, can't get prot status\n");
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return 1;
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}
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}
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/* issue the Read Identifier Codes command */
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*addr = (FPW) INTEL_READID;
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/* wait at least 35ns (W12) before reading */
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udelay(1);
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/* Intel example code uses offset of 2 for 16 bit flash */
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|
||||||
lock_conf_addr = (FPWV *) info->start[sector] + 2;
|
|
||||||
ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
|
|
||||||
|
|
||||||
/* put flash back in read mode */
|
|
||||||
*addr = (FPW) INTEL_RESET;
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
|
||||||
{
|
|
||||||
int flag, prot, sect;
|
|
||||||
ulong type, start;
|
|
||||||
int rcode = 0;
|
|
||||||
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) {
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("- missing\n");
|
|
||||||
} else {
|
|
||||||
printf ("- no sectors to erase\n");
|
|
||||||
}
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
type = (info->flash_id & FLASH_VENDMASK);
|
|
||||||
if ((type != FLASH_MAN_INTEL)) {
|
|
||||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
|
||||||
info->flash_id);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
prot = 0;
|
|
||||||
for (sect = s_first; sect <= s_last; ++sect) {
|
|
||||||
if (info->protect[sect]) {
|
|
||||||
prot++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (prot) {
|
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
|
||||||
prot);
|
|
||||||
} else {
|
|
||||||
printf ("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
start = get_timer (0);
|
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts ();
|
|
||||||
|
|
||||||
/* Start erase on unprotected sectors */
|
|
||||||
for (sect = s_first; sect <= s_last; sect++) {
|
|
||||||
if (info->protect[sect] == 0) { /* not protected */
|
|
||||||
FPWV *addr = (FPWV *) (info->start[sect]);
|
|
||||||
FPW status;
|
|
||||||
|
|
||||||
printf ("Erasing sector %2d ... ", sect);
|
|
||||||
|
|
||||||
/* arm simple, non interrupt dependent timer */
|
|
||||||
start = get_timer(0);
|
|
||||||
|
|
||||||
*addr = (FPW) 0x00500050; /* clear status register */
|
|
||||||
*addr = (FPW) 0x00200020; /* erase setup */
|
|
||||||
*addr = (FPW) 0x00D000D0; /* erase confirm */
|
|
||||||
|
|
||||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
|
||||||
printf ("Timeout\n");
|
|
||||||
*addr = (FPW) 0x00B000B0; /* suspend erase */
|
|
||||||
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
|
|
||||||
rcode = 1;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
*addr = 0x00500050; /* clear status register cmd. */
|
|
||||||
*addr = 0x00FF00FF; /* resest to read mode */
|
|
||||||
|
|
||||||
printf (" done\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
return rcode;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
* 4 - Flash not identified
|
|
||||||
*/
|
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
||||||
{
|
|
||||||
ulong cp, wp;
|
|
||||||
FPW data;
|
|
||||||
int count, i, l, rc, port_width;
|
|
||||||
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) {
|
|
||||||
return 4;
|
|
||||||
}
|
|
||||||
/* get lower word aligned address */
|
|
||||||
#ifdef FLASH_PORT_WIDTH16
|
|
||||||
wp = (addr & ~1);
|
|
||||||
port_width = 2;
|
|
||||||
#else
|
|
||||||
wp = (addr & ~3);
|
|
||||||
port_width = 4;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes
|
|
||||||
*/
|
|
||||||
if ((l = addr - wp) != 0) {
|
|
||||||
data = 0;
|
|
||||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *) cp);
|
|
||||||
}
|
|
||||||
for (; i < port_width && cnt > 0; ++i) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
--cnt;
|
|
||||||
++cp;
|
|
||||||
}
|
|
||||||
for (; cnt == 0 && i < port_width; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *) cp);
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
|
||||||
return (rc);
|
|
||||||
}
|
|
||||||
wp += port_width;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle word aligned part
|
|
||||||
*/
|
|
||||||
count = 0;
|
|
||||||
while (cnt >= port_width) {
|
|
||||||
data = 0;
|
|
||||||
for (i = 0; i < port_width; ++i) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
}
|
|
||||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
|
||||||
return (rc);
|
|
||||||
}
|
|
||||||
wp += port_width;
|
|
||||||
cnt -= port_width;
|
|
||||||
if (count++ > 0x800) {
|
|
||||||
spin_wheel ();
|
|
||||||
count = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (cnt == 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes
|
|
||||||
*/
|
|
||||||
data = 0;
|
|
||||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
--cnt;
|
|
||||||
}
|
|
||||||
for (; i < port_width; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *) cp);
|
|
||||||
}
|
|
||||||
|
|
||||||
return (write_data (info, wp, SWAP (data)));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word or halfword to Flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
static int write_data (flash_info_t *info, ulong dest, FPW data)
|
|
||||||
{
|
|
||||||
FPWV *addr = (FPWV *) dest;
|
|
||||||
ulong status;
|
|
||||||
ulong start;
|
|
||||||
int flag;
|
|
||||||
int rcode = 0;
|
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */
|
|
||||||
if ((*addr & data) != data) {
|
|
||||||
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
|
|
||||||
return (2);
|
|
||||||
}
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts ();
|
|
||||||
|
|
||||||
*addr = (FPW) 0x00400040; /* write setup */
|
|
||||||
*addr = data;
|
|
||||||
|
|
||||||
/* arm simple, non interrupt dependent timer */
|
|
||||||
start = get_timer(0);
|
|
||||||
|
|
||||||
/* wait while polling the status register */
|
|
||||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
|
||||||
rcode = 1;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
||||||
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
return rcode;
|
|
||||||
}
|
|
||||||
|
|
||||||
void inline spin_wheel (void)
|
|
||||||
{
|
|
||||||
static int p = 0;
|
|
||||||
static char w[] = "\\/-";
|
|
||||||
|
|
||||||
printf ("\010%c", w[p]);
|
|
||||||
(++p == 3) ? (p = 0) : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Set/Clear sector's lock bit, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - Error (timeout, voltage problems, etc.)
|
|
||||||
*/
|
|
||||||
int flash_real_protect (flash_info_t *info, long sector, int prot)
|
|
||||||
{
|
|
||||||
ulong start;
|
|
||||||
int i;
|
|
||||||
int rc = 0;
|
|
||||||
vu_long *addr = (vu_long *)(info->start[sector]);
|
|
||||||
int flag = disable_interrupts();
|
|
||||||
|
|
||||||
*addr = INTEL_CLEAR; /* Clear status register */
|
|
||||||
if (prot) { /* Set sector lock bit */
|
|
||||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
|
||||||
*addr = INTEL_PROTECT; /* set */
|
|
||||||
}
|
|
||||||
else { /* Clear sector lock bit */
|
|
||||||
*addr = INTEL_LOCKBIT; /* All sectors lock bits */
|
|
||||||
*addr = INTEL_CONFIRM; /* clear */
|
|
||||||
}
|
|
||||||
|
|
||||||
start = get_timer(0);
|
|
||||||
|
|
||||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
|
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
|
|
||||||
printf("Flash lock bit operation timed out\n");
|
|
||||||
rc = 1;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (*addr != INTEL_OK) {
|
|
||||||
printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
|
|
||||||
(uint)addr, (uint)*addr);
|
|
||||||
rc = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!rc)
|
|
||||||
info->protect[sector] = prot;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear lock bit command clears all sectors lock bits, so
|
|
||||||
* we have to restore lock bits of protected sectors.
|
|
||||||
* WARNING: code below re-locks sectors only for one bank (info).
|
|
||||||
* This causes problems on boards where several banks share
|
|
||||||
* the same chip, as sectors in othere banks will be unlocked
|
|
||||||
* but not re-locked. It works fine on pm520 though, as there
|
|
||||||
* is only one chip and one bank.
|
|
||||||
*/
|
|
||||||
if (!prot)
|
|
||||||
{
|
|
||||||
for (i = 0; i < info->sector_count; i++)
|
|
||||||
{
|
|
||||||
if (info->protect[i])
|
|
||||||
{
|
|
||||||
start = get_timer(0);
|
|
||||||
addr = (vu_long *)(info->start[i]);
|
|
||||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
|
||||||
*addr = INTEL_PROTECT; /* set */
|
|
||||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
|
|
||||||
{
|
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
|
|
||||||
{
|
|
||||||
printf("Flash lock bit operation timed out\n");
|
|
||||||
rc = 1;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/*
|
|
||||||
* get the s/w sector protection status in sync with the h/w,
|
|
||||||
* in case something went wrong during the re-locking.
|
|
||||||
*/
|
|
||||||
flash_sync_real_protect(info); /* resets flash to read mode */
|
|
||||||
}
|
|
||||||
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
*addr = INTEL_RESET; /* Reset to read array mode */
|
|
||||||
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2004
|
|
||||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SDRAM_DDR 1 /* is DDR */
|
|
||||||
|
|
||||||
/* Settings for XLB = 132 MHz */
|
|
||||||
#define SDRAM_MODE 0x018D0000
|
|
||||||
#define SDRAM_EMODE 0x40090000
|
|
||||||
#define SDRAM_CONTROL 0x714f0f00
|
|
||||||
#define SDRAM_CONFIG1 0x73722930
|
|
||||||
#define SDRAM_CONFIG2 0x47770000
|
|
||||||
#define SDRAM_TAPDELAY 0x10000000
|
|
||||||
|
|
@ -1,14 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2004
|
|
||||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SDRAM_DDR 0 /* is SDR */
|
|
||||||
|
|
||||||
/* Settings for XLB = 132 MHz */
|
|
||||||
#define SDRAM_MODE 0x00CD0000
|
|
||||||
#define SDRAM_CONTROL 0x504F0000
|
|
||||||
#define SDRAM_CONFIG1 0xD2322800
|
|
||||||
#define SDRAM_CONFIG2 0x8AD70000
|
|
||||||
|
|
@ -1,253 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2003-2004
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2004
|
|
||||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mpc5xxx.h>
|
|
||||||
#include <pci.h>
|
|
||||||
#include <netdev.h>
|
|
||||||
|
|
||||||
#if defined(CONFIG_MPC5200_DDR)
|
|
||||||
#include "mt46v16m16-75.h"
|
|
||||||
#else
|
|
||||||
#include "mt48lc16m16a2-75.h"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_RAMBOOT
|
|
||||||
static void sdram_start (int hi_addr)
|
|
||||||
{
|
|
||||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
|
||||||
|
|
||||||
/* unlock mode register */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* precharge all banks */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
#if SDRAM_DDR
|
|
||||||
/* set mode register: extended mode */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* set mode register: reset DLL */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* precharge all banks */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* auto refresh */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* set mode register */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* normal operation */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ATTENTION: Although partially referenced initdram does NOT make real use
|
|
||||||
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
|
|
||||||
* is something else than 0x00000000.
|
|
||||||
*/
|
|
||||||
|
|
||||||
phys_size_t initdram (int board_type)
|
|
||||||
{
|
|
||||||
ulong dramsize = 0;
|
|
||||||
ulong dramsize2 = 0;
|
|
||||||
#ifndef CONFIG_SYS_RAMBOOT
|
|
||||||
ulong test1, test2;
|
|
||||||
|
|
||||||
/* setup SDRAM chip selects */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
/* setup config registers */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
|
|
||||||
#if SDRAM_DDR
|
|
||||||
/* set tap delay */
|
|
||||||
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
|
|
||||||
__asm__ volatile ("sync");
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* find RAM size using SDRAM CS0 only */
|
|
||||||
sdram_start(0);
|
|
||||||
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
|
|
||||||
sdram_start(1);
|
|
||||||
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
|
|
||||||
if (test1 > test2) {
|
|
||||||
sdram_start(0);
|
|
||||||
dramsize = test1;
|
|
||||||
} else {
|
|
||||||
dramsize = test2;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* memory smaller than 1MB is impossible */
|
|
||||||
if (dramsize < (1 << 20)) {
|
|
||||||
dramsize = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* set SDRAM CS0 size according to the amount of RAM found */
|
|
||||||
if (dramsize > 0) {
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
|
|
||||||
} else {
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* let SDRAM CS1 start right after CS0 */
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
|
|
||||||
|
|
||||||
/* find RAM size using SDRAM CS1 only */
|
|
||||||
if (!dramsize)
|
|
||||||
sdram_start(0);
|
|
||||||
test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
|
||||||
if (!dramsize) {
|
|
||||||
sdram_start(1);
|
|
||||||
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
|
||||||
}
|
|
||||||
if (test1 > test2) {
|
|
||||||
sdram_start(0);
|
|
||||||
dramsize2 = test1;
|
|
||||||
} else {
|
|
||||||
dramsize2 = test2;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* memory smaller than 1MB is impossible */
|
|
||||||
if (dramsize2 < (1 << 20)) {
|
|
||||||
dramsize2 = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* set SDRAM CS1 size according to the amount of RAM found */
|
|
||||||
if (dramsize2 > 0) {
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
|
|
||||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
|
|
||||||
} else {
|
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* CONFIG_SYS_RAMBOOT */
|
|
||||||
|
|
||||||
/* retrieve size of memory connected to SDRAM CS0 */
|
|
||||||
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
|
|
||||||
if (dramsize >= 0x13) {
|
|
||||||
dramsize = (1 << (dramsize - 0x13)) << 20;
|
|
||||||
} else {
|
|
||||||
dramsize = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* retrieve size of memory connected to SDRAM CS1 */
|
|
||||||
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
|
|
||||||
if (dramsize2 >= 0x13) {
|
|
||||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
|
||||||
} else {
|
|
||||||
dramsize2 = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_SYS_RAMBOOT */
|
|
||||||
|
|
||||||
return dramsize + dramsize2;
|
|
||||||
}
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
puts ("Board: MicroSys PM520 \n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void flash_preinit(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Now, when we are in RAM, enable flash write
|
|
||||||
* access for detection process.
|
|
||||||
* Note that CS_BOOT cannot be cleared when
|
|
||||||
* executing in flash.
|
|
||||||
*/
|
|
||||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
|
||||||
}
|
|
||||||
|
|
||||||
void flash_afterinit(ulong start, ulong size)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_BOOT_ROM)
|
|
||||||
/* adjust mapping */
|
|
||||||
*(vu_long *)MPC5XXX_CS1_START =
|
|
||||||
START_REG(start);
|
|
||||||
*(vu_long *)MPC5XXX_CS1_STOP =
|
|
||||||
STOP_REG(start, size);
|
|
||||||
#else
|
|
||||||
/* adjust mapping */
|
|
||||||
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
|
|
||||||
START_REG(start);
|
|
||||||
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
|
|
||||||
STOP_REG(start, size);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
extern flash_info_t flash_info[]; /* info for FLASH chips */
|
|
||||||
|
|
||||||
int misc_init_r (void)
|
|
||||||
{
|
|
||||||
/* adjust flash start */
|
|
||||||
gd->bd->bi_flashstart = flash_info[0].start[0];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
static struct pci_controller hose;
|
|
||||||
|
|
||||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
|
||||||
|
|
||||||
void pci_init_board(void)
|
|
||||||
{
|
|
||||||
pci_mpc5xxx_init(&hose);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
|
|
||||||
|
|
||||||
void init_ide_reset (void)
|
|
||||||
{
|
|
||||||
debug ("init_ide_reset\n");
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void ide_set_reset (int idereset)
|
|
||||||
{
|
|
||||||
debug ("ide_reset(%d)\n", idereset);
|
|
||||||
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_DOC)
|
|
||||||
void doc_init (void)
|
|
||||||
{
|
|
||||||
doc_probe (CONFIG_SYS_DOC_BASE);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
cpu_eth_init(bis); /* Built in FEC comes first */
|
|
||||||
return pci_eth_init(bis);
|
|
||||||
}
|
|
||||||
|
|
@ -1,4 +0,0 @@
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
|
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_MPC5xxx=y
|
|
||||||
CONFIG_TARGET_PM520=y
|
|
||||||
|
|
@ -1,4 +0,0 @@
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,BOOT_ROM"
|
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_MPC5xxx=y
|
|
||||||
CONFIG_TARGET_PM520=y
|
|
||||||
|
|
@ -1,4 +0,0 @@
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
|
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_MPC5xxx=y
|
|
||||||
CONFIG_TARGET_PM520=y
|
|
||||||
|
|
@ -1,3 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_MPC5xxx=y
|
|
||||||
CONFIG_TARGET_PM520=y
|
|
||||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||||
|
|
||||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||||
=================================================================================================
|
=================================================================================================
|
||||||
|
PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
|
||||||
Total5200 powerpc mpc5xxx - -
|
Total5200 powerpc mpc5xxx - -
|
||||||
CATcenter powerpc ppc4xx - -
|
CATcenter powerpc ppc4xx - -
|
||||||
PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
|
PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
|
||||||
|
|
|
||||||
|
|
@ -1,342 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2003-2005
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
* (easy to change)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_MPC5200
|
|
||||||
#define CONFIG_PM520 1 /* PM520 board */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xfff00000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
|
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R
|
|
||||||
|
|
||||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial console configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
|
||||||
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PCI Mapping:
|
|
||||||
* 0x40000000 - 0x4fffffff - PCI Memory
|
|
||||||
* 0x50000000 - 0x50ffffff - PCI IO Space
|
|
||||||
*/
|
|
||||||
#define CONFIG_PCI 1
|
|
||||||
#define CONFIG_PCI_PNP 1
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW 1
|
|
||||||
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
|
|
||||||
|
|
||||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
|
||||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
|
||||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
|
||||||
|
|
||||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
|
||||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
|
||||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
|
||||||
|
|
||||||
#define CONFIG_MII 1
|
|
||||||
#define CONFIG_EEPRO100 1
|
|
||||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
|
||||||
#undef CONFIG_NS8382X
|
|
||||||
|
|
||||||
|
|
||||||
/* Partitions */
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
/* USB */
|
|
||||||
#if 1
|
|
||||||
#define CONFIG_USB_OHCI
|
|
||||||
#define CONFIG_USB_STORAGE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
#define CONFIG_BOOTP_BOOTPATH
|
|
||||||
#define CONFIG_BOOTP_GATEWAY
|
|
||||||
#define CONFIG_BOOTP_HOSTNAME
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_BEDBUG
|
|
||||||
#define CONFIG_CMD_DATE
|
|
||||||
#define CONFIG_CMD_DHCP
|
|
||||||
#define CONFIG_CMD_EEPROM
|
|
||||||
#define CONFIG_CMD_FAT
|
|
||||||
#define CONFIG_CMD_I2C
|
|
||||||
#define CONFIG_CMD_IDE
|
|
||||||
#define CONFIG_CMD_NFS
|
|
||||||
#define CONFIG_CMD_SNTP
|
|
||||||
#define CONFIG_CMD_USB
|
|
||||||
|
|
||||||
#define CONFIG_CMD_PCI
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Autobooting
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
|
||||||
|
|
||||||
#define CONFIG_PREBOOT "echo;" \
|
|
||||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
|
||||||
"echo"
|
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"hostname=pm520\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=${serverip}:${rootpath}\0" \
|
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
||||||
"addip=setenv bootargs ${bootargs} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
||||||
":${hostname}:${netdev}:off panic=1\0" \
|
|
||||||
"flash_nfs=run nfsargs addip;" \
|
|
||||||
"bootm ${kernel_addr}\0" \
|
|
||||||
"flash_self=run ramargs addip;" \
|
|
||||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
||||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
|
||||||
"rootpath=/opt/eldk30/ppc_82xx\0" \
|
|
||||||
"bootfile=/tftpboot/PM520/uImage\0" \
|
|
||||||
""
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IPB Bus clocking configuration.
|
|
||||||
*/
|
|
||||||
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
|
||||||
/*
|
|
||||||
* I2C configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
|
||||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
|
||||||
|
|
||||||
/*
|
|
||||||
* EEPROM configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RTC configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_RTC_PCF8563
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DOC_BASE 0xE0000000
|
|
||||||
#define CONFIG_SYS_DOC_SIZE 0x00100000
|
|
||||||
|
|
||||||
#if defined(CONFIG_BOOT_ROM)
|
|
||||||
/*
|
|
||||||
* Flash configuration (8,16 or 32 MB)
|
|
||||||
* TEXT base always at 0xFFF00000
|
|
||||||
* ENV_ADDR always at 0xFFF40000
|
|
||||||
* FLASH_BASE at 0xFA000000 for 64 MB
|
|
||||||
* 0xFC000000 for 32 MB
|
|
||||||
* 0xFD000000 for 16 MB
|
|
||||||
* 0xFD800000 for 8 MB
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFA000000
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000
|
|
||||||
#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
|
|
||||||
#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
|
|
||||||
#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
|
|
||||||
#else
|
|
||||||
/*
|
|
||||||
* Flash configuration (8,16 or 32 MB)
|
|
||||||
* TEXT base always at 0xFFF00000
|
|
||||||
* ENV_ADDR always at 0xFFF40000
|
|
||||||
* FLASH_BASE at 0xFC000000 for 64 MB
|
|
||||||
* 0xFE000000 for 32 MB
|
|
||||||
* 0xFF000000 for 16 MB
|
|
||||||
* 0xFF800000 for 8 MB
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000
|
|
||||||
#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
|
||||||
|
|
||||||
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
|
|
||||||
|
|
||||||
#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment settings
|
|
||||||
*/
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
||||||
#define CONFIG_ENV_SIZE 0x10000
|
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x40000
|
|
||||||
#define CONFIG_ENV_OVERWRITE 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_MBAR 0xf0000000
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
|
||||||
|
|
||||||
/* Use SRAM until RAM will be available */
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
|
||||||
# define CONFIG_SYS_RAMBOOT 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Ethernet configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_MPC5xxx_FEC 1
|
|
||||||
#define CONFIG_MPC5xxx_FEC_MII100
|
|
||||||
/*
|
|
||||||
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
|
|
||||||
*/
|
|
||||||
/* #define CONFIG_MPC5xxx_FEC_MII10 */
|
|
||||||
#define CONFIG_PHY_ADDR 0x00
|
|
||||||
|
|
||||||
/*
|
|
||||||
* GPIO configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Various low-level settings
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
|
||||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
|
||||||
|
|
||||||
#if defined(CONFIG_BOOT_ROM)
|
|
||||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
|
|
||||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
|
|
||||||
#define CONFIG_SYS_BOOTCS_CFG 0x00047800
|
|
||||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
|
|
||||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
|
|
||||||
#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
|
|
||||||
#define CONFIG_SYS_CS1_CFG 0x0004FF00
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
|
||||||
#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
|
|
||||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
|
||||||
#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
|
|
||||||
#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
|
|
||||||
#define CONFIG_SYS_CS1_CFG 0x00047800
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
|
||||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* USB stuff
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_USB_CLOCK 0x0001BBBB
|
|
||||||
#define CONFIG_USB_CONFIG 0x00005000
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* IDE/ATA stuff Supports IDE harddisk
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
|
||||||
|
|
||||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
|
||||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
|
||||||
|
|
||||||
#undef CONFIG_IDE_RESET /* reset for ide supported */
|
|
||||||
#define CONFIG_IDE_PREINIT
|
|
||||||
|
|
||||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
|
||||||
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
|
|
||||||
|
|
||||||
/* Offset for data I/O */
|
|
||||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
|
|
||||||
|
|
||||||
/* Offset for normal register accesses */
|
|
||||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
|
||||||
|
|
||||||
/* Offset for alternate registers */
|
|
||||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
|
|
||||||
|
|
||||||
/* Interval between registers */
|
|
||||||
#define CONFIG_SYS_ATA_STRIDE 4
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
Loading…
Reference in New Issue