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Merge git://git.denx.de/u-boot-pxa

This commit is contained in:
Tom Rini 2015-03-02 07:24:15 -05:00
parent 6fa361903c 44ba7a373a
commit a1b341989b
16 changed files with 47 additions and 61 deletions
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2
board/balloon3/balloon3.c
View File

@ -29,7 +29,7 @@ int board_init(void)
dcache_disable();
icache_disable();
/* arch number of vpac270 */
/* arch number of balloon3 */
gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
/* adress of boot parameters */

2
board/toradex/colibri_pxa270/colibri_pxa270.c
View File

@ -23,7 +23,7 @@ int board_init(void)
dcache_disable();
icache_disable();
/* arch number of vpac270 */
/* arch number of Toradex Colibri PXA270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
/* adress of boot parameters */

10
include/configs/balloon3.h
View File

@ -13,7 +13,7 @@
* High Level Board Configuration Options
*/
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_BALLOON3 1 /* Balloon3 board */
#define CONFIG_BALLOON3 1 /* Balloon3 board */
/*
* Environment settings
@ -84,18 +84,17 @@
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*
* DRAM Map
*/
#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
@ -135,7 +134,7 @@
#define CONFIG_ENV_IS_IN_FLASH
#else
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x000000
@ -191,7 +190,6 @@
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
#define CONFIG_SYS_MEM_BUF_IMP 0x0f
/*
* PCMCIA and CF Interfaces

77
include/configs/colibri_pxa270.h
View File

@ -2,18 +2,22 @@
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0x0
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT 0x40000
/*
* Environment settings
@ -22,13 +26,13 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
"if fatload mmc 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"bootm 0x80000;"
"bootm 0xc0000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
@ -50,6 +54,8 @@
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_LOADB /* Both together */
#undef CONFIG_CMD_LOADS /* saves 10 KB */
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
@ -59,7 +65,6 @@
/*
* Networking Configuration
* chip on the Voipac PXA270 board
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
@ -82,7 +87,7 @@
*/
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP
#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
@ -96,7 +101,6 @@
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
/*
* Clock Configuration
*/
@ -142,25 +146,24 @@
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MONITOR_LEN 0x80000
#define CONFIG_SYS_MONITOR_LEN 0x40000
/* Skip factory configuration block */
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
#define CONFIG_ENV_SIZE 0x40000
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* GPIO settings
*/
#define CONFIG_SYS_GPSR0_VAL 0x00000000
#define CONFIG_SYS_GPSR1_VAL 0x00020000
#define CONFIG_SYS_GPSR2_VAL 0x0002C000
#define CONFIG_SYS_GPSR2_VAL 0x0002c000
#define CONFIG_SYS_GPSR3_VAL 0x00000000
#define CONFIG_SYS_GPCR0_VAL 0x00000000
@ -168,19 +171,19 @@
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0x08000000
#define CONFIG_SYS_GPDR1_VAL 0x0002A981
#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
#define CONFIG_SYS_GPDR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xc8008000
#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
#define CONFIG_SYS_GPDR3_VAL 0x0061e804
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
#define CONFIG_SYS_PSSR_VAL 0x30
@ -193,26 +196,26 @@
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x000095f2
#define CONFIG_SYS_MSC1_VAL 0x00007ff4
#define CONFIG_SYS_MSC2_VAL 0x00000000
#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
#define CONFIG_SYS_MDMRS_VAL 0x00320032
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
#define CONFIG_SYS_MDREFR_VAL 0x2003a031
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000001
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
#define CONFIG_SYS_MECR_VAL 0x00000000
#define CONFIG_SYS_MCMEM0_VAL 0x00028307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
#define CONFIG_SYS_MCATT0_VAL 0x00038787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
#define CONFIG_SYS_MCIO0_VAL 0x0002830f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
#include "pxa-common.h"
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */

2
include/configs/flea3.h
View File

@ -124,8 +124,6 @@
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*

2
include/configs/mx35pdk.h
View File

@ -146,8 +146,6 @@
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*

1
include/configs/palmld.h
View File

@ -114,7 +114,6 @@
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*

1
include/configs/palmtc.h
View File

@ -116,7 +116,6 @@
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
/*

1
include/configs/palmtreo680.h
View File

@ -117,7 +117,6 @@
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*

1
include/configs/snowball.h
View File

@ -175,7 +175,6 @@
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1

1
include/configs/ti816x_evm.h
View File

@ -58,7 +58,6 @@
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_CMD_ASKEN

1
include/configs/u8500_href.h
View File

@ -131,7 +131,6 @@
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE

1
include/configs/vexpress_common.h
View File

@ -188,7 +188,6 @@
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
#define CONFIG_BOOTDELAY 2

3
include/configs/vpac270.h
View File

@ -221,7 +221,7 @@
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_NOWHERE
#endif
/*
@ -297,7 +297,6 @@
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
#define CONFIG_SYS_MEM_BUF_IMP 0x0f
/*
* PCMCIA and CF Interfaces

2
include/configs/woodburn_common.h
View File

@ -146,8 +146,6 @@
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*

1
include/configs/zipitz2.h
View File

@ -136,7 +136,6 @@ unsigned char zipitz2_spi_read(void);
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*