From 23b93e1d66e19a3e23ac2dadff9a3135744bcd29 Mon Sep 17 00:00:00 2001
From: Matt Waddel <matt.waddel@linaro.org>
Date: Sat, 16 Apr 2011 11:54:07 +0000
Subject: [PATCH 1/7] MMC: Add support for PL180 ARM mmc device
Add support for the ARM PrimeCell MultiMedia Interface - PL180.
Ported from original device driver written by ST-Ericsson.
Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
---
drivers/mmc/Makefile | 1 +
drivers/mmc/arm_pl180_mmci.c | 441 +++++++++++++++++++++++++++++++++++
drivers/mmc/arm_pl180_mmci.h | 183 +++++++++++++++
3 files changed, 625 insertions(+)
create mode 100644 drivers/mmc/arm_pl180_mmci.c
create mode 100644 drivers/mmc/arm_pl180_mmci.h
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9aca3a2bd6..a8fe17a6f7 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
+COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
new file mode 100644
index 0000000000..245f48294c
--- /dev/null
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -0,0 +1,441 @@
+/*
+ * ARM PrimeCell MultiMedia Card Interface - PL180
+ *
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Ulf Hansson <ulf.hansson@stericsson.com>
+ * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
+ * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <asm/io.h>
+#include "common.h"
+#include <errno.h>
+#include <mmc.h>
+#include "arm_pl180_mmci.h"
+#include <malloc.h>
+
+struct mmc_host {
+ struct sdi_registers *base;
+};
+
+static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
+{
+ u32 hoststatus, statusmask;
+ struct mmc_host *host = dev->priv;
+
+ statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
+ if ((cmd->resp_type & MMC_RSP_PRESENT))
+ statusmask |= SDI_STA_CMDREND;
+ else
+ statusmask |= SDI_STA_CMDSENT;
+
+ do
+ hoststatus = readl(&host->base->status) & statusmask;
+ while (!hoststatus);
+
+ writel(statusmask, &host->base->status_clear);
+ if (hoststatus & SDI_STA_CTIMEOUT) {
+ printf("CMD%d time out\n", cmd->cmdidx);
+ return -ETIMEDOUT;
+ } else if ((hoststatus & SDI_STA_CCRCFAIL) &&
+ (cmd->flags & MMC_RSP_CRC)) {
+ printf("CMD%d CRC error\n", cmd->cmdidx);
+ return -EILSEQ;
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ cmd->response[0] = readl(&host->base->response0);
+ cmd->response[1] = readl(&host->base->response1);
+ cmd->response[2] = readl(&host->base->response2);
+ cmd->response[3] = readl(&host->base->response3);
+ debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
+ "response[2]:0x%08X, response[3]:0x%08X\n",
+ cmd->cmdidx, cmd->response[0], cmd->response[1],
+ cmd->response[2], cmd->response[3]);
+ }
+
+ return 0;
+}
+
+/* send command to the mmc card and wait for results */
+static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
+{
+ int result;
+ u32 sdi_cmd = 0;
+ struct mmc_host *host = dev->priv;
+
+ sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
+
+ if (cmd->resp_type) {
+ sdi_cmd |= SDI_CMD_WAITRESP;
+ if (cmd->resp_type & MMC_RSP_136)
+ sdi_cmd |= SDI_CMD_LONGRESP;
+ }
+
+ writel((u32)cmd->cmdarg, &host->base->argument);
+ udelay(COMMAND_REG_DELAY);
+ writel(sdi_cmd, &host->base->command);
+ result = wait_for_command_end(dev, cmd);
+
+ /* After CMD2 set RCA to a none zero value. */
+ if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
+ dev->rca = 10;
+
+ /* After CMD3 open drain is switched off and push pull is used. */
+ if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
+ u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
+ writel(sdi_pwr, &host->base->power);
+ }
+
+ return result;
+}
+
+static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
+{
+ u32 *tempbuff = dest;
+ int i;
+ u64 xfercount = blkcount * blksize;
+ struct mmc_host *host = dev->priv;
+ u32 status, status_err;
+
+ debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
+
+ status = readl(&host->base->status);
+ status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
+ SDI_STA_RXOVERR);
+ while (!status_err &&
+ (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32))) {
+ if (status & SDI_STA_RXFIFOBR) {
+ for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
+ *(tempbuff + i) = readl(&host->base->fifo);
+ tempbuff += SDI_FIFO_BURST_SIZE;
+ xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
+ }
+ status = readl(&host->base->status);
+ status_err = status &
+ (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR);
+ }
+
+ if (status & SDI_STA_DTIMEOUT) {
+ printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
+ xfercount, status);
+ return -ETIMEDOUT;
+ } else if (status & SDI_STA_DCRCFAIL) {
+ printf("Read data blk CRC error: 0x%x\n", status);
+ return -EILSEQ;
+ } else if (status & SDI_STA_RXOVERR) {
+ printf("Read data RX overflow error\n");
+ return -EIO;
+ }
+
+ while ((!status_err) && (xfercount >= sizeof(u32))) {
+ if (status & SDI_STA_RXDAVL) {
+ *(tempbuff) = readl(&host->base->fifo);
+ tempbuff++;
+ xfercount -= sizeof(u32);
+ }
+ status = readl(&host->base->status);
+ status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
+ SDI_STA_RXOVERR);
+ }
+
+ status_err = status &
+ (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
+ SDI_STA_RXOVERR);
+ while (!status_err) {
+ status = readl(&host->base->status);
+ status_err = status &
+ (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
+ SDI_STA_RXOVERR);
+ }
+
+ if (status & SDI_STA_DTIMEOUT) {
+ printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
+ xfercount, status);
+ return -ETIMEDOUT;
+ } else if (status & SDI_STA_DCRCFAIL) {
+ printf("Read data bytes CRC error: 0x%x\n", status);
+ return -EILSEQ;
+ } else if (status & SDI_STA_RXOVERR) {
+ printf("Read data RX overflow error\n");
+ return -EIO;
+ }
+
+ writel(SDI_ICR_MASK, &host->base->status_clear);
+
+ if (xfercount) {
+ printf("Read data error, xfercount: %llu\n", xfercount);
+ return -ENOBUFS;
+ }
+
+ return 0;
+}
+
+static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
+{
+ u32 *tempbuff = src;
+ int i;
+ u64 xfercount = blkcount * blksize;
+ struct mmc_host *host = dev->priv;
+ u32 status, status_err;
+
+ debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
+
+ status = readl(&host->base->status);
+ status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
+ while (!status_err && xfercount) {
+ if (status & SDI_STA_TXFIFOBW) {
+ if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
+ for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
+ writel(*(tempbuff + i),
+ &host->base->fifo);
+ tempbuff += SDI_FIFO_BURST_SIZE;
+ xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
+ } else {
+ while (xfercount >= sizeof(u32)) {
+ writel(*(tempbuff), &host->base->fifo);
+ tempbuff++;
+ xfercount -= sizeof(u32);
+ }
+ }
+ }
+ status = readl(&host->base->status);
+ status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
+ }
+
+ status_err = status &
+ (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
+ while (!status_err) {
+ status = readl(&host->base->status);
+ status_err = status &
+ (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
+ }
+
+ if (status & SDI_STA_DTIMEOUT) {
+ printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
+ xfercount, status);
+ return -ETIMEDOUT;
+ } else if (status & SDI_STA_DCRCFAIL) {
+ printf("Write data CRC error\n");
+ return -EILSEQ;
+ }
+
+ writel(SDI_ICR_MASK, &host->base->status_clear);
+
+ if (xfercount) {
+ printf("Write data error, xfercount:%llu", xfercount);
+ return -ENOBUFS;
+ }
+
+ return 0;
+}
+
+static int do_data_transfer(struct mmc *dev,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ int error = -ETIMEDOUT;
+ struct mmc_host *host = dev->priv;
+ u32 blksz = 0;
+ u32 data_ctrl = 0;
+ u32 data_len = (u32) (data->blocks * data->blocksize);
+
+ blksz = (ffs(data->blocksize) - 1);
+ data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
+ data_ctrl |= SDI_DCTRL_DTEN;
+
+ writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
+ writel(data_len, &host->base->datalength);
+ udelay(DATA_REG_DELAY);
+
+ if (data->flags & MMC_DATA_READ) {
+ data_ctrl |= SDI_DCTRL_DTDIR_IN;
+ writel(data_ctrl, &host->base->datactrl);
+
+ error = do_command(dev, cmd);
+ if (error)
+ return error;
+
+ error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
+ (u32)data->blocksize);
+ } else if (data->flags & MMC_DATA_WRITE) {
+ error = do_command(dev, cmd);
+ if (error)
+ return error;
+
+ writel(data_ctrl, &host->base->datactrl);
+ error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
+ (u32)data->blocksize);
+ }
+
+ return error;
+}
+
+static int host_request(struct mmc *dev,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ int result;
+
+ if (data)
+ result = do_data_transfer(dev, cmd, data);
+ else
+ result = do_command(dev, cmd);
+
+ return result;
+}
+
+/* MMC uses open drain drivers in the enumeration phase */
+static int mmc_host_reset(struct mmc *dev)
+{
+ struct mmc_host *host = dev->priv;
+ u32 sdi_u32 = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
+
+ writel(sdi_u32, &host->base->power);
+
+ return 0;
+}
+
+static void host_set_ios(struct mmc *dev)
+{
+ struct mmc_host *host = dev->priv;
+ u32 sdi_clkcr;
+
+ sdi_clkcr = readl(&host->base->clock);
+
+ /* Ramp up the clock rate */
+ if (dev->clock) {
+ u32 clkdiv = 0;
+
+ if (dev->clock >= dev->f_max)
+ dev->clock = dev->f_max;
+
+ clkdiv = ((ARM_MCLK / dev->clock) / 2) - 1;
+
+ if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
+ clkdiv = SDI_CLKCR_CLKDIV_MASK;
+
+ sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
+ sdi_clkcr |= clkdiv;
+ }
+
+ /* Set the bus width */
+ if (dev->bus_width) {
+ u32 buswidth = 0;
+
+ switch (dev->bus_width) {
+ case 1:
+ buswidth |= SDI_CLKCR_WIDBUS_1;
+ break;
+ case 4:
+ buswidth |= SDI_CLKCR_WIDBUS_4;
+ break;
+ default:
+ printf("Invalid bus width\n");
+ break;
+ }
+ sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
+ sdi_clkcr |= buswidth;
+ }
+
+ writel(sdi_clkcr, &host->base->clock);
+ udelay(CLK_CHANGE_DELAY);
+}
+
+struct mmc *alloc_mmc_struct(void)
+{
+ struct mmc_host *host = NULL;
+ struct mmc *mmc_device = NULL;
+
+ host = malloc(sizeof(struct mmc_host));
+ if (!host)
+ return NULL;
+
+ mmc_device = malloc(sizeof(struct mmc));
+ if (!mmc_device)
+ goto err;
+
+ mmc_device->priv = host;
+ return mmc_device;
+
+err:
+ free(host);
+ return NULL;
+}
+
+/*
+ * mmc_host_init - initialize the mmc controller.
+ * Set initial clock and power for mmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int arm_pl180_mmci_host_init(struct mmc *dev)
+{
+ struct mmc_host *host = dev->priv;
+ u32 sdi_u32;
+
+ host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+
+ /* Initially set power-on, full voltage & MMCI read */
+ sdi_u32 = INIT_PWR;
+ writel(sdi_u32, &host->base->power);
+
+ /* setting clk freq 505KHz */
+ sdi_u32 = SDI_CLKCR_CLKDIV_INIT | SDI_CLKCR_CLKEN;
+ writel(sdi_u32, &host->base->clock);
+ udelay(CLK_CHANGE_DELAY);
+
+ /* Disable mmc interrupts */
+ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
+ writel(sdi_u32, &host->base->mask0);
+
+ sprintf(dev->name, "MMC");
+ dev->clock = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT + 1));
+ dev->send_cmd = host_request;
+ dev->set_ios = host_set_ios;
+ dev->init = mmc_host_reset;
+ dev->host_caps = 0;
+ dev->voltages = VOLTAGE_WINDOW_MMC;
+ dev->f_min = dev->clock;
+ dev->f_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
+
+ return 0;
+}
+
+int arm_pl180_mmci_init(void)
+{
+ int error;
+ struct mmc *dev;
+
+ dev = alloc_mmc_struct();
+ if (!dev)
+ return -1;
+
+ error = arm_pl180_mmci_host_init(dev);
+ if (error) {
+ printf("mmci_host_init error - %d\n", error);
+ return -1;
+ }
+
+ mmc_register(dev);
+ debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
+
+ return 0;
+}
diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h
new file mode 100644
index 0000000000..42fbe3e386
--- /dev/null
+++ b/drivers/mmc/arm_pl180_mmci.h
@@ -0,0 +1,183 @@
+/*
+ * ARM PrimeCell MultiMedia Card Interface - PL180
+ *
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Ulf Hansson <ulf.hansson@stericsson.com>
+ * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
+ * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_PL180_MMCI_H__
+#define __ARM_PL180_MMCI_H__
+
+int arm_pl180_mmci_init(void);
+
+#define COMMAND_REG_DELAY 300
+#define DATA_REG_DELAY 1000
+#define CLK_CHANGE_DELAY 2000
+
+#define INIT_PWR 0xBF /* Power on, full power, not open drain */
+#define ARM_MCLK (100*1000*1000)
+
+/* SDI Power Control register bits */
+#define SDI_PWR_PWRCTRL_MASK 0x00000003
+#define SDI_PWR_PWRCTRL_ON 0x00000003
+#define SDI_PWR_PWRCTRL_OFF 0x00000000
+#define SDI_PWR_DAT2DIREN 0x00000004
+#define SDI_PWR_CMDDIREN 0x00000008
+#define SDI_PWR_DAT0DIREN 0x00000010
+#define SDI_PWR_DAT31DIREN 0x00000020
+#define SDI_PWR_OPD 0x00000040
+#define SDI_PWR_FBCLKEN 0x00000080
+#define SDI_PWR_DAT74DIREN 0x00000100
+#define SDI_PWR_RSTEN 0x00000200
+
+#define VOLTAGE_WINDOW_MMC 0x00FF8080
+#define VOLTAGE_WINDOW_SD 0x80010000
+
+/* SDI clock control register bits */
+#define SDI_CLKCR_CLKDIV_MASK 0x000000FF
+#define SDI_CLKCR_CLKEN 0x00000100
+#define SDI_CLKCR_PWRSAV 0x00000200
+#define SDI_CLKCR_BYPASS 0x00000400
+#define SDI_CLKCR_WIDBUS_MASK 0x00001800
+#define SDI_CLKCR_WIDBUS_1 0x00000000
+#define SDI_CLKCR_WIDBUS_4 0x00000800
+
+#define SDI_CLKCR_CLKDIV_INIT 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
+
+/* SDI command register bits */
+#define SDI_CMD_CMDINDEX_MASK 0x000000FF
+#define SDI_CMD_WAITRESP 0x00000040
+#define SDI_CMD_LONGRESP 0x00000080
+#define SDI_CMD_WAITINT 0x00000100
+#define SDI_CMD_WAITPEND 0x00000200
+#define SDI_CMD_CPSMEN 0x00000400
+#define SDI_CMD_SDIOSUSPEND 0x00000800
+#define SDI_CMD_ENDCMDCOMPL 0x00001000
+#define SDI_CMD_NIEN 0x00002000
+#define SDI_CMD_CE_ATACMD 0x00004000
+#define SDI_CMD_CBOOTMODEEN 0x00008000
+
+#define SDI_DTIMER_DEFAULT 0xFFFF0000
+
+/* SDI Status register bits */
+#define SDI_STA_CCRCFAIL 0x00000001
+#define SDI_STA_DCRCFAIL 0x00000002
+#define SDI_STA_CTIMEOUT 0x00000004
+#define SDI_STA_DTIMEOUT 0x00000008
+#define SDI_STA_TXUNDERR 0x00000010
+#define SDI_STA_RXOVERR 0x00000020
+#define SDI_STA_CMDREND 0x00000040
+#define SDI_STA_CMDSENT 0x00000080
+#define SDI_STA_DATAEND 0x00000100
+#define SDI_STA_STBITERR 0x00000200
+#define SDI_STA_DBCKEND 0x00000400
+#define SDI_STA_CMDACT 0x00000800
+#define SDI_STA_TXACT 0x00001000
+#define SDI_STA_RXACT 0x00002000
+#define SDI_STA_TXFIFOBW 0x00004000
+#define SDI_STA_RXFIFOBR 0x00008000
+#define SDI_STA_TXFIFOF 0x00010000
+#define SDI_STA_RXFIFOF 0x00020000
+#define SDI_STA_TXFIFOE 0x00040000
+#define SDI_STA_RXFIFOE 0x00080000
+#define SDI_STA_TXDAVL 0x00100000
+#define SDI_STA_RXDAVL 0x00200000
+#define SDI_STA_SDIOIT 0x00400000
+#define SDI_STA_CEATAEND 0x00800000
+#define SDI_STA_CARDBUSY 0x01000000
+#define SDI_STA_BOOTMODE 0x02000000
+#define SDI_STA_BOOTACKERR 0x04000000
+#define SDI_STA_BOOTACKTIMEOUT 0x08000000
+#define SDI_STA_RSTNEND 0x10000000
+
+/* SDI Interrupt Clear register bits */
+#define SDI_ICR_MASK 0x1DC007FF
+#define SDI_ICR_CCRCFAILC 0x00000001
+#define SDI_ICR_DCRCFAILC 0x00000002
+#define SDI_ICR_CTIMEOUTC 0x00000004
+#define SDI_ICR_DTIMEOUTC 0x00000008
+#define SDI_ICR_TXUNDERRC 0x00000010
+#define SDI_ICR_RXOVERRC 0x00000020
+#define SDI_ICR_CMDRENDC 0x00000040
+#define SDI_ICR_CMDSENTC 0x00000080
+#define SDI_ICR_DATAENDC 0x00000100
+#define SDI_ICR_STBITERRC 0x00000200
+#define SDI_ICR_DBCKENDC 0x00000400
+#define SDI_ICR_SDIOITC 0x00400000
+#define SDI_ICR_CEATAENDC 0x00800000
+#define SDI_ICR_BUSYENDC 0x01000000
+#define SDI_ICR_BOOTACKERRC 0x04000000
+#define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
+#define SDI_ICR_RSTNENDC 0x10000000
+
+#define SDI_MASK0_MASK 0x1FFFFFFF
+
+/* SDI Data control register bits */
+#define SDI_DCTRL_DTEN 0x00000001
+#define SDI_DCTRL_DTDIR_IN 0x00000002
+#define SDI_DCTRL_DTMODE_STREAM 0x00000004
+#define SDI_DCTRL_DMAEN 0x00000008
+#define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
+#define SDI_DCTRL_RWSTART 0x00000100
+#define SDI_DCTRL_RWSTOP 0x00000200
+#define SDI_DCTRL_RWMOD 0x00000200
+#define SDI_DCTRL_SDIOEN 0x00000800
+#define SDI_DCTRL_DMAREQCTL 0x00001000
+#define SDI_DCTRL_DBOOTMODEEN 0x00002000
+#define SDI_DCTRL_BUSYMODE 0x00004000
+#define SDI_DCTRL_DDR_MODE 0x00008000
+
+#define SDI_FIFO_BURST_SIZE 8
+
+struct sdi_registers {
+ u32 power; /* 0x00*/
+ u32 clock; /* 0x04*/
+ u32 argument; /* 0x08*/
+ u32 command; /* 0x0c*/
+ u32 respcommand; /* 0x10*/
+ u32 response0; /* 0x14*/
+ u32 response1; /* 0x18*/
+ u32 response2; /* 0x1c*/
+ u32 response3; /* 0x20*/
+ u32 datatimer; /* 0x24*/
+ u32 datalength; /* 0x28*/
+ u32 datactrl; /* 0x2c*/
+ u32 datacount; /* 0x30*/
+ u32 status; /* 0x34*/
+ u32 status_clear; /* 0x38*/
+ u32 mask0; /* 0x3c*/
+ u32 mask1; /* 0x40*/
+ u32 card_select; /* 0x44*/
+ u32 fifo_count; /* 0x48*/
+ u32 padding1[(0x80-0x4C)>>2];
+ u32 fifo; /* 0x80*/
+ u32 padding2[(0xFE0-0x84)>>2];
+ u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
+ u32 periph_id1; /* 0xFE4*/
+ u32 periph_id2; /* 0xFE8*/
+ u32 periph_id3; /* 0xFEC*/
+ u32 pcell_id0; /* 0xFF0*/
+ u32 pcell_id1; /* 0xFF4*/
+ u32 pcell_id2; /* 0xFF8*/
+ u32 pcell_id3; /* 0xFFC*/
+};
+
+#endif
From f0c64526b7e51ba997a0f1baf9e74e6d497b957e Mon Sep 17 00:00:00 2001
From: Matt Waddel <matt.waddel@linaro.org>
Date: Sat, 16 Apr 2011 11:54:08 +0000
Subject: [PATCH 2/7] ARMV7: Vexpress: Add MMC support
Added the board specific definitions to use the MMCI device.
Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
---
board/armltd/vexpress/ca9x4_ct_vxp.c | 9 +++++++++
include/configs/ca9x4_ct_vxp.h | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c
index ce1be1e766..3566b958e7 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -86,6 +86,15 @@ int board_eth_init(bd_t *bis)
return rc;
}
+int cpu_mmc_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_ARM_PL180_MMCI
+ rc = arm_pl180_mmci_init();
+#endif
+ return rc;
+}
+
static void flash__init(void)
{
/* Setup the sytem control register to allow writing to flash */
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 2a87a798d5..c6fac32dbb 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -87,6 +87,10 @@
#define CONFIG_MMC 1
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE 0x10005000
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
From 28df15e0234a773cfec98c2775915abe1472db3c Mon Sep 17 00:00:00 2001
From: Thomas Chou <thomas@wytron.com.tw>
Date: Sun, 17 Apr 2011 21:00:46 +0000
Subject: [PATCH 3/7] mmc_spi: add mmc_init call
As Andy Fleming suggested, we can call mmc_init() in mmc_spi command.
So that we don't need to run mmcinfo command next.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
common/cmd_mmc_spi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/cmd_mmc_spi.c b/common/cmd_mmc_spi.c
index 63fe313377..cfd0fb1136 100644
--- a/common/cmd_mmc_spi.c
+++ b/common/cmd_mmc_spi.c
@@ -74,6 +74,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev,
bus, cs, speed, mode);
+ mmc_init(mmc);
return 0;
usage:
From 8feafcc49c0b7a9c541904f95a43dbef2fecc38b Mon Sep 17 00:00:00 2001
From: John Rigby <john.rigby@linaro.org>
Date: Mon, 18 Apr 2011 05:50:08 +0000
Subject: [PATCH 4/7] MMC: make b_max unconditional
Make existing field b_max field in struct mmc unconditional
and use it instead of CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_bread
and mmc_bwrite.
Initialize b_max to CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_register
if it has not been initialized by the hw driver.
Initialize b_max to 0 in all callers to mmc_register.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
drivers/mmc/arm_pl180_mmci.c | 2 ++
drivers/mmc/bfin_sdh.c | 2 ++
drivers/mmc/davinci_mmc.c | 3 +--
drivers/mmc/gen_atmel_mci.c | 2 ++
drivers/mmc/mmc.c | 8 ++++----
drivers/mmc/mxcmmc.c | 2 ++
drivers/mmc/omap_hsmmc.c | 2 ++
drivers/mmc/s5p_mmc.c | 1 +
include/mmc.h | 2 --
9 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index 245f48294c..ed296ee026 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -434,6 +434,8 @@ int arm_pl180_mmci_init(void)
return -1;
}
+ dev->b_max = 0;
+
mmc_register(dev);
debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 31b6459373..bc9057fa9a 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -257,6 +257,8 @@ int bfin_mmc_init(bd_t *bis)
mmc->f_min = mmc->f_max >> 9;
mmc->block_dev.part_type = PART_TYPE_DOS;
+ mmc->b_max = 0;
+
mmc_register(mmc);
return 0;
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index d5d19ebee3..5d918e6ffc 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -394,9 +394,8 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
mmc->voltages = host->voltages;
mmc->host_caps = host->host_caps;
-#ifdef CONFIG_MMC_MBLOCK
mmc->b_max = DAVINCI_MAX_BLOCKS;
-#endif
+
mmc_register(mmc);
return 0;
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 2984d645c9..6577925b8e 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -348,6 +348,8 @@ int atmel_mci_init(void *regs)
mmc->f_min = get_mci_clk_rate() / (2*256);
mmc->f_max = get_mci_clk_rate() / (2*1);
+ mmc->b_max = 0;
+
mmc_register(mmc);
return 0;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f27b7c79e5..f6d31f5848 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -243,8 +243,7 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
return 0;
do {
- cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ?
- CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo;
+ cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
if(mmc_write_blocks(mmc, start, cur, src) != cur)
return 0;
blocks_todo -= cur;
@@ -320,8 +319,7 @@ static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
return 0;
do {
- cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ?
- CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo;
+ cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
if(mmc_read_blocks(mmc, dst, start, cur) != cur)
return 0;
blocks_todo -= cur;
@@ -1029,6 +1027,8 @@ int mmc_register(struct mmc *mmc)
mmc->block_dev.removable = 1;
mmc->block_dev.block_read = mmc_bread;
mmc->block_dev.block_write = mmc_bwrite;
+ if (!mmc->b_max)
+ mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
INIT_LIST_HEAD (&mmc->link);
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
index 59639539f3..ab1fc82fbb 100644
--- a/drivers/mmc/mxcmmc.c
+++ b/drivers/mmc/mxcmmc.c
@@ -511,6 +511,8 @@ static int mxcmci_initialize(bd_t *bis)
mmc->f_min = imx_get_perclk2() >> 7;
mmc->f_max = imx_get_perclk2() >> 1;
+ mmc->b_max = 0;
+
mmc_register(mmc);
return 0;
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 6f2280abff..dcbde8935a 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -465,6 +465,8 @@ int omap_mmc_init(int dev_index)
mmc->f_min = 400000;
mmc->f_max = 52000000;
+ mmc->b_max = 0;
+
mmc_register(mmc);
return 0;
diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c
index 0323800711..668c28bded 100644
--- a/drivers/mmc/s5p_mmc.c
+++ b/drivers/mmc/s5p_mmc.c
@@ -466,6 +466,7 @@ static int s5p_mmc_initialize(int dev_index, int bus_width)
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
+ mmc->m_bmax = 0;
mmc_register(mmc);
return 0;
diff --git a/include/mmc.h b/include/mmc.h
index e0a56d9d23..b4197a72f4 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -283,9 +283,7 @@ struct mmc {
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
-#ifdef CONFIG_MMC_MBLOCK
uint b_max;
-#endif
};
int mmc_register(struct mmc *mmc);
From 4ca9244d74f146a0605f5bee28a66e39aae88d3e Mon Sep 17 00:00:00 2001
From: John Rigby <john.rigby@linaro.org>
Date: Tue, 19 Apr 2011 05:48:14 +0000
Subject: [PATCH 5/7] MMC: omap_hsmmc.c: disable multiblock rw on old rev
omap34xx silicon
Signed-off-by: John Rigby <john.rigby@linaro.org>
---
drivers/mmc/omap_hsmmc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index dcbde8935a..957b9877a0 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -467,6 +467,14 @@ int omap_mmc_init(int dev_index)
mmc->b_max = 0;
+#if defined(CONFIG_OMAP34XX)
+ /*
+ * Silicon revs 2.1 and older do not support multiblock transfers.
+ */
+ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
+ mmc->b_max = 1;
+#endif
+
mmc_register(mmc);
return 0;
From 4571de33ee99d746f114d45b78283782adb01a3f Mon Sep 17 00:00:00 2001
From: Jason Liu <jason.hui@linaro.org>
Date: Tue, 22 Mar 2011 01:32:31 +0000
Subject: [PATCH 6/7] fsl_esdhc: Fix multi-block read restriction on i.MX53
eSDHCv2
For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need
to be set to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in i.MX53 reference manual:
29.7.8 Multi-block Read
For pre-defined multi-block read operation, that is,the number of blocks
to read has been defined by previous CMD23 for MMC, or pre-defined number
of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without
abort command at card side, an abort command, either automatic or manual
CMD12/CMD52, is still required by ESDHC after the pre-defined number of
blocks are done, to drive the internal state machine to idle mode. In this
case, the card may not respond to this extra abort command and ESDHC will
get Response Timeout. It is recommended to manually send an abort command
with RSPTYP[1:0] both bits cleared.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
---
drivers/mmc/fsl_esdhc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 2838795feb..d2355be6b0 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -99,6 +99,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
+#ifdef CONFIG_MX53
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ xfertyp |= XFERTYP_CMDTYP_ABORT;
+#endif
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}
From abe2c93ffb13d58985503595e0151bf03a4a6c2a Mon Sep 17 00:00:00 2001
From: Thomas Chou <thomas@wytron.com.tw>
Date: Tue, 19 Apr 2011 03:48:31 +0000
Subject: [PATCH 7/7] mmc: coding style fix and tabify of mmc.h
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
include/mmc.h | 44 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/mmc.h b/include/mmc.h
index b4197a72f4..f7f2286981 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -94,14 +94,14 @@
#define MMC_HS_TIMING 0x00000100
#define MMC_HS_52MHZ 0x2
-#define OCR_BUSY 0x80000000
-#define OCR_HCS 0x40000000
+#define OCR_BUSY 0x80000000
+#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
#define MMC_STATUS_MASK (~0x0206BF7F)
-#define MMC_STATUS_RDY_FOR_DATA (1<<8)
-#define MMC_STATUS_CURR_STATE (0xf<<9)
+#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
+#define MMC_STATUS_CURR_STATE (0xf << 9)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
@@ -147,12 +147,12 @@
* EXT_CSD field definitions
*/
-#define EXT_CSD_CMD_SET_NORMAL (1<<0)
-#define EXT_CSD_CMD_SET_SECURE (1<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
+#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
+#define EXT_CSD_CMD_SET_SECURE (1 << 1)
+#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
-#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
@@ -162,21 +162,21 @@
#define R1_APP_CMD (1 << 5)
#define MMC_RSP_PRESENT (1 << 0)
-#define MMC_RSP_136 (1 << 1) /* 136 bit response */
-#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
-#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
-#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
+#define MMC_RSP_136 (1 << 1) /* 136 bit response */
+#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
+#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
+#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
-#define MMC_RSP_NONE (0)
-#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_NONE (0)
+#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
MMC_RSP_BUSY)
-#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
-#define MMC_RSP_R3 (MMC_RSP_PRESENT)
-#define MMC_RSP_R4 (MMC_RSP_PRESENT)
-#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
-#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
-#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3 (MMC_RSP_PRESENT)
+#define MMC_RSP_R4 (MMC_RSP_PRESENT)
+#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
struct mmc_cid {