Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
commit
9cddb4fe02
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@ -197,6 +197,19 @@ int sata_init(void)
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}
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}
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#endif
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#endif
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static void erratum_a009929(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
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struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
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u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
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rstrqmr1 |= 0x00000400;
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gur_out32(&gur->rstrqmr1, rstrqmr1);
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writel(0x01000000, dcsr_cop_ccp);
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#endif
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}
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void fsl_lsch2_early_init_f(void)
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void fsl_lsch2_early_init_f(void)
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{
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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@ -216,6 +229,9 @@ void fsl_lsch2_early_init_f(void)
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*/
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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/* Erratum */
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erratum_a009929();
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}
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}
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#endif
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#endif
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@ -166,6 +166,7 @@
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#define GICD_BASE 0x01401000
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#define GICC_BASE 0x01402000
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#define CONFIG_SYS_FSL_ERRATUM_A009929
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#else
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#else
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#error SoC not defined
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#error SoC not defined
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#endif
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#endif
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@ -11,7 +11,8 @@
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_DCSRBAR 0x20000000
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#define CONFIG_SYS_DCSRBAR 0x20000000
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#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
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#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
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#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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@ -1,7 +1,7 @@
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#PBL preamble and RCW header
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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aa55aa55 01ee0100
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# serdes protocol
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# serdes protocol
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0810000f 0c000000 00000000 00000000
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08100010 0a000000 00000000 00000000
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14550002 80004012 e0106000 61002000
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14550002 80004012 e0106000 c1002000
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00000000 00000000 00000000 00038800
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00000000 00000000 00000000 00038800
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00000000 00001100 00000096 00000001
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00000000 00001100 00000096 00000001
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@ -2,7 +2,7 @@
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aa55aa55 01ee0100
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aa55aa55 01ee0100
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# RCW
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# RCW
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# Enable IFC; disable QSPI
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# Enable IFC; disable QSPI
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0810000f 0c000000 00000000 00000000
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08100010 0a000000 00000000 00000000
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14550002 80004012 60040000 61002000
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14550002 80004012 60040000 c1002000
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00000000 00000000 00000000 00038800
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00000000 00000000 00000000 00038800
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00000000 00001100 00000096 00000001
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00000000 00001100 00000096 00000001
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@ -1,7 +1,7 @@
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#PBL preamble and RCW header
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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aa55aa55 01ee0100
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# serdes protocol
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# serdes protocol
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0810000f 0c000000 00000000 00000000
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08100010 0a000000 00000000 00000000
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14550002 80004012 e0106000 61002000
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14550002 80004012 e0106000 c1002000
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00000000 00000000 00000000 00038800
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00000000 00000000 00000000 00038800
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00000000 00001100 00000096 00000001
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00000000 00001100 00000096 00000001
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@ -1,7 +1,7 @@
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#PBL preamble and RCW header
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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aa55aa55 01ee0100
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# RCW
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# RCW
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0810000f 0c000000 00000000 00000000
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08100010 0a000000 00000000 00000000
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14550002 80004012 60040000 61002000
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14550002 80004012 60040000 c1002000
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00000000 00000000 00000000 00038800
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00000000 00000000 00000000 00038800
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00000000 00001100 00000096 00000001
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00000000 00001100 00000096 00000001
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@ -242,8 +242,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
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int off;
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int off;
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uint32_t ph;
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uint32_t ph;
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phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
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phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
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#ifndef CONFIG_SYS_FMAN_V3
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u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
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u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
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CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
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CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
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#endif
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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if (off == -FDT_ERR_NOTFOUND)
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if (off == -FDT_ERR_NOTFOUND)
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@ -295,8 +297,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
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/* board code might have caused offset to change */
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/* board code might have caused offset to change */
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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#ifndef CONFIG_SYS_FMAN_V3
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/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
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/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
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if (paddr != dtsec1_addr)
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if (paddr != dtsec1_addr)
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#endif
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fdt_status_disabled(blob, off); /* disable the MAC node */
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fdt_status_disabled(blob, off); /* disable the MAC node */
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/* disable the fsl,dpa-ethernet node that points to the MAC */
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/* disable the fsl,dpa-ethernet node that points to the MAC */
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@ -54,11 +54,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port)) {
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if (is_device_disabled(port))
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printf("%s:%d: port(%d) is disabled\n", __func__,
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__LINE__, port);
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return PHY_INTERFACE_MODE_NONE;
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return PHY_INTERFACE_MODE_NONE;
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}
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if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
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if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
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return PHY_INTERFACE_MODE_XGMII;
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return PHY_INTERFACE_MODE_XGMII;
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@ -69,15 +66,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
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if (port == FM1_DTSEC3)
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if (port == FM1_DTSEC3)
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
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FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
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FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
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printf("%s:%d: port(FM1_DTSEC3) is OK\n",
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__func__, __LINE__);
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return PHY_INTERFACE_MODE_RGMII;
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return PHY_INTERFACE_MODE_RGMII;
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}
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}
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if (port == FM1_DTSEC4)
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if (port == FM1_DTSEC4)
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
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FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
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FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
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printf("%s:%d: port(FM1_DTSEC4) is OK\n",
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__func__, __LINE__);
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return PHY_INTERFACE_MODE_RGMII;
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return PHY_INTERFACE_MODE_RGMII;
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}
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}
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@ -541,19 +541,6 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
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goto out;
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goto out;
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}
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}
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if (MC_VER_MAJOR != mc_ver_info.major) {
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printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
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mc_ver_info.major, MC_VER_MAJOR);
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printf("fsl-mc: Update the Management Complex firmware\n");
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error = -ENODEV;
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goto out;
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}
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if (MC_VER_MINOR != mc_ver_info.minor)
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printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
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mc_ver_info.minor, MC_VER_MINOR);
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printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
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printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
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mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
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mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
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reg_gsr & GSR_FS_MASK);
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reg_gsr & GSR_FS_MASK);
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