Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini 2015-12-17 07:52:56 -05:00
commit 9cddb4fe02
10 changed files with 32 additions and 30 deletions

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@ -197,6 +197,19 @@ int sata_init(void)
} }
#endif #endif
static void erratum_a009929(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
rstrqmr1 |= 0x00000400;
gur_out32(&gur->rstrqmr1, rstrqmr1);
writel(0x01000000, dcsr_cop_ccp);
#endif
}
void fsl_lsch2_early_init_f(void) void fsl_lsch2_early_init_f(void)
{ {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@ -216,6 +229,9 @@ void fsl_lsch2_early_init_f(void)
*/ */
out_le32(&cci->slave[4].snoop_ctrl, out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
/* Erratum */
erratum_a009929();
} }
#endif #endif

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@ -166,6 +166,7 @@
#define GICD_BASE 0x01401000 #define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000 #define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_ERRATUM_A009929
#else #else
#error SoC not defined #error SoC not defined
#endif #endif

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@ -11,7 +11,8 @@
#define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)

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@ -1,7 +1,7 @@
#PBL preamble and RCW header #PBL preamble and RCW header
aa55aa55 01ee0100 aa55aa55 01ee0100
# serdes protocol # serdes protocol
0810000f 0c000000 00000000 00000000 08100010 0a000000 00000000 00000000
14550002 80004012 e0106000 61002000 14550002 80004012 e0106000 c1002000
00000000 00000000 00000000 00038800 00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001 00000000 00001100 00000096 00000001

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@ -2,7 +2,7 @@
aa55aa55 01ee0100 aa55aa55 01ee0100
# RCW # RCW
# Enable IFC; disable QSPI # Enable IFC; disable QSPI
0810000f 0c000000 00000000 00000000 08100010 0a000000 00000000 00000000
14550002 80004012 60040000 61002000 14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800 00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001 00000000 00001100 00000096 00000001

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@ -1,7 +1,7 @@
#PBL preamble and RCW header #PBL preamble and RCW header
aa55aa55 01ee0100 aa55aa55 01ee0100
# serdes protocol # serdes protocol
0810000f 0c000000 00000000 00000000 08100010 0a000000 00000000 00000000
14550002 80004012 e0106000 61002000 14550002 80004012 e0106000 c1002000
00000000 00000000 00000000 00038800 00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001 00000000 00001100 00000096 00000001

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@ -1,7 +1,7 @@
#PBL preamble and RCW header #PBL preamble and RCW header
aa55aa55 01ee0100 aa55aa55 01ee0100
# RCW # RCW
0810000f 0c000000 00000000 00000000 08100010 0a000000 00000000 00000000
14550002 80004012 60040000 61002000 14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800 00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001 00000000 00001100 00000096 00000001

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@ -242,8 +242,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
int off; int off;
uint32_t ph; uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr); off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (off == -FDT_ERR_NOTFOUND) if (off == -FDT_ERR_NOTFOUND)
@ -295,8 +297,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
/* board code might have caused offset to change */ /* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr); off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
#ifndef CONFIG_SYS_FMAN_V3
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr) if (paddr != dtsec1_addr)
#endif
fdt_status_disabled(blob, off); /* disable the MAC node */ fdt_status_disabled(blob, off); /* disable the MAC node */
/* disable the fsl,dpa-ethernet node that points to the MAC */ /* disable the fsl,dpa-ethernet node that points to the MAC */

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@ -54,11 +54,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) { if (is_device_disabled(port))
printf("%s:%d: port(%d) is disabled\n", __func__,
__LINE__, port);
return PHY_INTERFACE_MODE_NONE; return PHY_INTERFACE_MODE_NONE;
}
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII; return PHY_INTERFACE_MODE_XGMII;
@ -69,15 +66,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
if (port == FM1_DTSEC3) if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
printf("%s:%d: port(FM1_DTSEC3) is OK\n",
__func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII; return PHY_INTERFACE_MODE_RGMII;
} }
if (port == FM1_DTSEC4) if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
printf("%s:%d: port(FM1_DTSEC4) is OK\n",
__func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII; return PHY_INTERFACE_MODE_RGMII;
} }

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@ -541,19 +541,6 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
goto out; goto out;
} }
if (MC_VER_MAJOR != mc_ver_info.major) {
printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
mc_ver_info.major, MC_VER_MAJOR);
printf("fsl-mc: Update the Management Complex firmware\n");
error = -ENODEV;
goto out;
}
if (MC_VER_MINOR != mc_ver_info.minor)
printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
mc_ver_info.minor, MC_VER_MINOR);
printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
reg_gsr & GSR_FS_MASK); reg_gsr & GSR_FS_MASK);