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sunxi: Support PSCI ops on Allwinner H3 

H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Chen-Yu Tsai 2016-01-06 15:13:08 +08:00 committed by Hans de Goede
parent ed80584f30
commit 9683945179
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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@ -106,7 +106,7 @@ psci_fiq_enter:
str r10, [r8, #0x100] str r10, [r8, #0x100]
timer_wait r10, ONE_MS timer_wait r10, ONE_MS
#ifdef CONFIG_MACH_SUN6I #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Activate power clamp @ Activate power clamp
lsl r12, r9, #2 @ x4 lsl r12, r9, #2 @ x4
add r12, r12, r8 add r12, r12, r8
@ -170,7 +170,7 @@ psci_cpu_on:
movw r0, #(SUNXI_PRCM_BASE & 0xffff) movw r0, #(SUNXI_PRCM_BASE & 0xffff)
movt r0, #(SUNXI_PRCM_BASE >> 16) movt r0, #(SUNXI_PRCM_BASE >> 16)
#ifdef CONFIG_MACH_SUN6I #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Release power clamp @ Release power clamp
lsl r5, r1, #2 @ 1 register per CPU lsl r5, r1, #2 @ 1 register per CPU
add r5, r5, r0 @ PRCM add r5, r5, r0 @ PRCM