xes: Use common PCI initialization code
Common Freescale code for PCI initialization now exists, so migrate X-ES boards to use it. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Peter Tyser
Kumar Gala
parent
4c66447ae7
commit
9660c5de74
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@ -25,10 +25,10 @@
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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int first_free_busno = 0;
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_MPC8572
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/* Correlate host/agent POR bits to usable info. Table 4-14 */
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struct host_agent_cfg_t {
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uchar pcie_root[3];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{0, 0, 0}, 0},
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{{0, 1, 1}, 1},
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{{1, 0, 1}, 0},
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{{1, 1, 0}, 1},
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{{0, 0, 1}, 0},
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{{0, 1, 0}, 1},
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{{1, 0, 0}, 0},
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{{1, 1, 1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-15 */
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struct io_port_cfg_t {
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uchar pcie_width[3];
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uchar rio_width;
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} io_port_cfg[16] = {
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 0},
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{{4, 4, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 4},
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{{4, 2, 2}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 4},
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{{4, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{8, 0, 0}, 0},
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};
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#elif defined CONFIG_MPC8548
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/* Correlate host/agent POR bits to usable info. Table 4-12 */
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struct host_agent_cfg_t {
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uchar pci_host[2];
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uchar pcie_root[1];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{1, 1}, {0}, 0},
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{{1, 1}, {1}, 0},
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{{1, 1}, {0}, 1},
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{{0, 0}, {0}, 0}, /* reserved */
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{{0, 1}, {1}, 0},
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{{1, 1}, {1}, 0},
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{{0, 1}, {1}, 1},
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{{1, 1}, {1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-13 */
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struct io_port_cfg_t {
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uchar pcie_width[1];
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uchar rio_width;
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} io_port_cfg[8] = {
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{{0}, 0},
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{{0}, 0},
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{{0}, 0},
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{{4}, 4},
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{{4}, 4},
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{{0}, 4},
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{{0}, 4},
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{{8}, 0},
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};
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#elif defined CONFIG_MPC86xx
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/* Correlate host/agent POR bits to usable info. Table 4-17 */
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struct host_agent_cfg_t {
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uchar pcie_root[2];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{0, 0}, 0},
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{{1, 0}, 1},
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{{0, 1}, 0},
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{{1, 1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-16 */
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struct io_port_cfg_t {
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uchar pcie_width[2];
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uchar rio_width;
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} io_port_cfg[16] = {
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{{0, 0}, 0},
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{{0, 0}, 0},
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{{8, 0}, 0},
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{{8, 8}, 0},
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{{0, 0}, 0},
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{{8, 0}, 4},
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{{8, 0}, 4},
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{{8, 0}, 4},
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{{0, 0}, 0},
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{{0, 0}, 4},
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{{0, 0}, 4},
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{{0, 0}, 4},
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{{0, 0}, 0},
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{{0, 0}, 0},
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{{0, 8}, 0},
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{{8, 8}, 0},
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};
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#endif
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/*
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* 85xx and 86xx share naming conventions, but different layout.
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* Correlate names to CPU-specific values to share common
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@ -173,22 +68,22 @@ struct io_port_cfg_t {
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void pci_init_board(void)
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{
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struct pci_controller *hose;
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volatile ccsr_fsl_pci_t *pci;
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int width;
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int host;
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struct fsl_pci_info pci_info[3];
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep;
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__maybe_unused int pcie_configured;
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#elif defined(CONFIG_MPC86xx)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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#endif
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uint devdisr = in_be32(&gur->devdisr);
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uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
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u32 devdisr = in_be32(&gur->devdisr);
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u32 pordevsr = in_be32(&gur->pordevsr);
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__maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
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MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
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uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
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MPC8xxx_PORBMSR_HA_SHIFT;
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struct pci_region *r;
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#ifdef CONFIG_PCI1
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uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
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@ -197,49 +92,19 @@ void pci_init_board(void)
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uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
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uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
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width = 0; /* Silence compiler warning... */
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io_sel &= 0xf; /* Silence compiler warning... */
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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hose = &pci1_hose;
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host = host_agent_cfg[host_agent].pci_host[0];
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r = hose->regions;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
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pci_32 ? 32 : 64,
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pcix ? "PCIX" : "PCI",
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pci_spd_norm ? ">=" : "<=",
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pcix ? freq * 2 : freq,
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host ? "host" : "agent",
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pcie_ep ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCI1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf(" PCI1: disabled\n");
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}
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@ -247,148 +112,53 @@ void pci_init_board(void)
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/* PCI1 not present on MPC8572 */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
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#endif
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#ifdef CONFIG_PCIE1
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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host = host_agent_cfg[host_agent].pcie_root[0];
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width = io_port_cfg[io_sel].pcie_width[0];
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r = hose->regions;
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
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printf("\n PCIE1 connected as %s (x%d)",
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host ? "Root Complex" : "Endpoint", width);
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if (in_be32(&pci->pme_msg_det)) {
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out_be32(&pci->pme_msg_det, 0xffffffff);
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debug(" with errors. Clearing. Now 0x%08x",
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in_be32(&pci->pme_msg_det));
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}
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printf("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf(" PCIE1 connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf(" PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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hose = &pcie2_hose;
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host = host_agent_cfg[host_agent].pcie_root[1];
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width = io_port_cfg[io_sel].pcie_width[1];
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r = hose->regions;
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
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printf("\n PCIE2 connected as %s (x%d)",
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host ? "Root Complex" : "Endpoint", width);
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if (in_be32(&pci->pme_msg_det)) {
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out_be32(&pci->pme_msg_det, 0xffffffff);
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debug(" with errors. Clearing. Now 0x%08x",
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in_be32(&pci->pme_msg_det));
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}
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printf("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BASE,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BASE,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE2 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf(" PCIE2 connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf(" PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
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#endif /* CONFIG_PCIE2 */
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#ifdef CONFIG_PCIE3
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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hose = &pcie3_hose;
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host = host_agent_cfg[host_agent].pcie_root[2];
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width = io_port_cfg[io_sel].pcie_width[2];
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r = hose->regions;
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
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if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
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printf("\n PCIE3 connected as %s (x%d)",
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host ? "Root Complex" : "Endpoint", width);
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if (in_be32(&pci->pme_msg_det)) {
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out_be32(&pci->pme_msg_det, 0xffffffff);
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debug(" with errors. Clearing. Now 0x%08x",
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in_be32(&pci->pme_msg_det));
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}
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printf("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BASE,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BASE,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE3 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf(" PCIE3 connected as %s\n",
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pcie_ep ? "Endpoint" : "Root Complex");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf(" PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
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@ -324,18 +324,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* PCIE1 - PEX8518 */
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#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
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/* PCIE2 - VPX P1 */
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
|
|
|
|||
|
|
@ -268,10 +268,10 @@
|
|||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
|
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
|
||||
|
||||
|
|
|
|||
|
|
@ -334,18 +334,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
/* PCIE1 - VPX P1 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
/* PCIE2 - PEX8518 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue