edminiv2: switch to SPL
ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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/*
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* (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on:
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*
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Based on omap-common/u-boot-spl.lds:
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
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LENGTH = CONFIG_SPL_MAX_SIZE }
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MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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.text :
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{
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__start = .;
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*(.vectors)
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CPUDIR/start.o (.text)
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*(.text*)
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} > .nor
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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} > .nor
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. = ALIGN(4);
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__image_copy_end = .;
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_end = .;
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} > .bss
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}
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@ -0,0 +1,10 @@
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/*
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* (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SPL_H_
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#define _ASM_ARCH_SPL_H_
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#define BOOT_DEVICE_NOR 1
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@ -5,6 +5,7 @@ choice
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config TARGET_EDMINIV2
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config TARGET_EDMINIV2
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bool "LaCie Ethernet Disk mini V2"
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bool "LaCie Ethernet Disk mini V2"
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select SUPPORT_SPL
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endchoice
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endchoice
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@ -234,7 +234,9 @@ int arch_cpu_init(void)
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/* Enable and invalidate L2 cache in write through mode */
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/* Enable and invalidate L2 cache in write through mode */
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invalidate_l2_cache();
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invalidate_l2_cache();
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#ifdef CONFIG_SPL_BUILD
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orion5x_config_adr_windows();
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orion5x_config_adr_windows();
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#endif
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return 0;
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return 0;
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}
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}
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/*
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/*
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* Low-level init happens right after start.S has switched to SVC32,
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* Low-level init happens right after start.S has switched to SVC32,
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* flushed and disabled caches and disabled MMU. We're still running
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* flushed and disabled caches and disabled MMU. We're still running
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* from the boot chip select, so the first thing we should do is set
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* from the boot chip select, so the first thing SPL should do is to
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* up RAM for us to relocate into.
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* set up the RAM to copy U-Boot into.
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*/
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*/
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.globl lowlevel_init
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.globl lowlevel_init
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lowlevel_init:
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lowlevel_init:
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#ifdef CONFIG_SPL_BUILD
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/* Use 'r4 as the base for internal register accesses */
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/* Use 'r4 as the base for internal register accesses */
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ldr r4, =ORION5X_REGS_PHY_BASE
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ldr r4, =ORION5X_REGS_PHY_BASE
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@ -273,5 +275,13 @@ lowlevel_init:
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orr r2, r2, r6
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orr r2, r2, r6
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str r2, [r3, #0x484]
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str r2, [r3, #0x484]
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/* enable for 2 GB DDR; detection should find out real amount */
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sub r6, r6, r6
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str r6, [r3, #0x500]
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ldr r6, =0x7fff0001
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str r6, [r3, #0x504]
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#endif /* CONFIG_SPL_BUILD */
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/* Return to U-boot via saved link register */
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/* Return to U-boot via saved link register */
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mov pc, lr
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mov pc, lr
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@ -12,6 +12,8 @@
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#include <miiphy.h>
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#include <miiphy.h>
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#include <asm/arch/orion5x.h>
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#include <asm/arch/orion5x.h>
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#include "../common/common.h"
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#include "../common/common.h"
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#include <spl.h>
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#include <ns16550.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -83,3 +85,21 @@ void reset_phy(void)
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mv_phy_88e1116_init("egiga0", 8);
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mv_phy_88e1116_init("egiga0", 8);
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}
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}
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#endif /* CONFIG_RESET_PHY_R */
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#endif /* CONFIG_RESET_PHY_R */
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/*
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* SPL serial setup and NOR boot device selection
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*/
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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preloader_console_init();
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NOR;
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}
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#endif /* CONFIG_SPL_BUILD */
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CONFIG_ARM=y
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CONFIG_SPL=y
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CONFIG_ORION5X=y
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+S:CONFIG_ARM=y
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CONFIG_TARGET_EDMINIV2=y
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+S:CONFIG_ORION5X=y
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+S:CONFIG_TARGET_EDMINIV2=y
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#define _CONFIG_EDMINIV2_H
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#define _CONFIG_EDMINIV2_H
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/* general settings */
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/* general settings */
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#define CONFIG_SYS_TEXT_BASE 0xfff90000
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* SPL
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*/
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NOR_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0xffff0000
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#define CONFIG_SPL_MAX_SIZE 0x0000fff0
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#define CONFIG_SPL_STACK 0x00020000
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#define CONFIG_SPL_BSS_START_ADDR 0x00020000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
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#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_UBOOT_BASE 0xfff90000
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#define CONFIG_SYS_UBOOT_START 0x00800000
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#define CONFIG_SYS_TEXT_BASE 0x00800000
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/*
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/*
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* Version number information
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* Version number information
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*/
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*/
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