pxa: fixing get_timer to return time in miliseconds.
Fixing the get_timer function to return time in miliseconds instead of ticks. Also fixed PXA boards to use the conventional value of 1000 for CONFIG_SYS_HZ. Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
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e5e88c3614
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94a3312920
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@ -33,6 +33,14 @@
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#error: interrupts not implemented yet
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#error: interrupts not implemented yet
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#endif
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#endif
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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#define TIMER_FREQ_HZ 3250000
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#elif defined(CONFIG_PXA250)
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#define TIMER_FREQ_HZ 3686400
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#else
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#error "Timer frequency unknown - please config PXA CPU type"
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#endif
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int interrupt_init (void)
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int interrupt_init (void)
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{
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{
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/* nothing happens here - we don't setup any IRQs */
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/* nothing happens here - we don't setup any IRQs */
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@ -67,7 +75,10 @@ void reset_timer_masked (void)
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ulong get_timer_masked (void)
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ulong get_timer_masked (void)
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{
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{
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return OSCR;
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unsigned long long ticks = get_ticks();
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return (((ticks / TIMER_FREQ_HZ) * 1000) +
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((ticks % TIMER_FREQ_HZ) * 1000) / TIMER_FREQ_HZ);
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}
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}
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void udelay_masked (unsigned long usec)
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void udelay_masked (unsigned long usec)
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@ -78,17 +89,17 @@ void udelay_masked (unsigned long usec)
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if (usec >= 1000) {
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo *= TIMER_FREQ_HZ;
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tmo /= 1000;
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tmo /= 1000;
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} else {
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} else {
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tmo = usec * CONFIG_SYS_HZ;
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tmo = usec * TIMER_FREQ_HZ;
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tmo /= (1000*1000);
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tmo /= (1000*1000);
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}
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}
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endtime = get_timer_masked () + tmo;
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endtime = get_ticks() + tmo;
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do {
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do {
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ulong now = get_timer_masked ();
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ulong now = get_ticks();
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diff = endtime - now;
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diff = endtime - now;
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} while (diff >= 0);
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} while (diff >= 0);
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}
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}
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@ -99,7 +110,7 @@ void udelay_masked (unsigned long usec)
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*/
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*/
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unsigned long long get_ticks(void)
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unsigned long long get_ticks(void)
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{
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{
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return get_timer(0);
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return OSCR;
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}
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}
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/*
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/*
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@ -109,6 +120,6 @@ unsigned long long get_ticks(void)
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ulong get_tbclk (void)
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ulong get_tbclk (void)
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{
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{
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ulong tbclk;
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ulong tbclk;
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tbclk = CONFIG_SYS_HZ;
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tbclk = TIMER_FREQ_HZ;
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return tbclk;
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return tbclk;
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}
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}
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@ -117,7 +117,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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@ -103,7 +103,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* valid baudrates */
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/* valid baudrates */
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@ -131,7 +131,7 @@
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/* RS: is this where U-Boot is */
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/* RS: is this where U-Boot is */
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/* RS: relocated to in RAM? */
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/* RS: relocated to in RAM? */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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/* RS: the oscillator is actually 3680130?? */
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/* RS: the oscillator is actually 3680130?? */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* 0101000001 */
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/* 0101000001 */
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@ -171,7 +171,7 @@
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */
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#define CONFIG_SYS_HZ 1000
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/* Monahans Core Frequency */
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/* Monahans Core Frequency */
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
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@ -119,7 +119,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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/* RS: the oscillator is actually 3680130?? */
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/* RS: the oscillator is actually 3680130?? */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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@ -112,7 +112,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */
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#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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/* RS: the oscillator is actually 3680130?? */
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/* RS: the oscillator is actually 3680130?? */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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@ -127,7 +127,7 @@
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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/* valid baudrates */
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/* valid baudrates */
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@ -126,7 +126,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* valid baudrates */
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/* valid baudrates */
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@ -241,7 +241,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define RTC 1 /* enable 32KHz osc */
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#define RTC 1 /* enable 32KHz osc */
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@ -168,7 +168,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
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#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
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/* valid baudrates */
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/* valid baudrates */
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@ -81,7 +81,7 @@
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#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */
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#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
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#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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@ -138,7 +138,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
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/*
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/*
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@ -121,7 +121,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
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/* valid baudrates */
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/* valid baudrates */
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_DOS_PARTITION 1
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#define BOARD_LATE_INIT 1
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#define BOARD_LATE_INIT 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_HZ 1000
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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@ -143,7 +143,7 @@
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */
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#define CONFIG_SYS_HZ 1000
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/* Monahans Core Frequency */
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/* Monahans Core Frequency */
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
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