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spi: ti_qspi: Fix baudrate divider calculation 

Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Vignesh R 2016-11-05 16:05:16 +05:30 committed by Tom Rini
parent 84295f2a20
commit 948b8bbd5f
1 changed files with 7 additions and 9 deletions
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16
drivers/spi/ti_qspi.c
View File

@ -16,6 +16,7 @@
#include <asm/omap_gpio.h> #include <asm/omap_gpio.h>
#include <asm/omap_common.h> #include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h> #include <asm/ti-common/ti-edma3.h>
#include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
if (!hz) if (!hz)
clk_div = 0; clk_div = 0;
else else
clk_div = (priv->fclk / hz) - 1; clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
/* truncate clk_div value to QSPI_CLK_DIV_MAX */
if (clk_div > QSPI_CLK_DIV_MAX)
clk_div = QSPI_CLK_DIV_MAX;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
/* disable SCLK */ /* disable SCLK */
writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
&priv->base->clk_ctrl); &priv->base->clk_ctrl);
/* enable SCLK and program the clk divider */
/* assign clk_div values */
if (clk_div < 0)
clk_div = 0;
else if (clk_div > QSPI_CLK_DIV_MAX)
clk_div = QSPI_CLK_DIV_MAX;
/* enable SCLK */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
} }