Add support for the Calao SBC35-A9G20 board
The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems <http://www.calao-systems.com>. It is built around an AT91SAM9G20 ARM SoC running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND flash, two USB host ports, and an USB device port. More informations can be found at <http://www.calao-systems.com/articles.php?lng=en&pg=5936> Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
This commit is contained in:
Albin Tonnerre
Jean-Christophe PLAGNIOL-VILLARD
parent
10bc241dfc
commit
9453967e28
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@ -690,6 +690,10 @@ Andrea Scian <andrea.scian@dave-tech.it>
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B2 ARM7TDMI (S3C44B0X)
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B2 ARM7TDMI (S3C44B0X)
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Albin Tonnerre <albin.tonnerre@free-electrons.com>
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sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
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Greg Ungerer <greg.ungerer@opengear.com>
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Greg Ungerer <greg.ungerer@opengear.com>
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cm4008 ks8695p
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cm4008 ks8695p
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1
MAKEALL
1
MAKEALL
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@ -613,6 +613,7 @@ LIST_at91=" \
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m501sk \
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m501sk \
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pm9261 \
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pm9261 \
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pm9263 \
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pm9263 \
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SBC35_A9G20 \
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"
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"
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#########################################################################
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#########################################################################
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7
Makefile
7
Makefile
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@ -2897,6 +2897,13 @@ at91sam9g45ekes_config : unconfig
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pm9263_config : unconfig
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pm9263_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
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@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
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SBC35_A9G20_NANDFLASH_config \
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SBC35_A9G20_EEPROM_config \
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SBC35_A9G20_config : unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
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@$(MKCONFIG) -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
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########################################################################
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########################################################################
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## ARM Integrator boards - see doc/README-integrator for more info.
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## ARM Integrator boards - see doc/README-integrator for more info.
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integratorap_config \
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integratorap_config \
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@ -0,0 +1,55 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian.pop@leadtechdesign.com>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += sbc35_a9g20.o
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COBJS-$(CONFIG_ATMEL_SPI) += spi.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1 @@
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TEXT_BASE = 0x23f00000
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@ -0,0 +1,197 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Copyright (C) 2009
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* Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void sbc35_a9g20_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void sbc35_a9g20_macb_hw_init(void)
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{
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unsigned long rstc;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA17) => PHY normal mode (not Test mode)
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* ERX0 (PA14) => PHY ADDR0
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* ERX1 (PA15) => PHY ADDR1
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* ERX2 (PA25) => PHY ADDR2
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* ERX3 (PA26) => PHY ADDR3
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* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_macb_hw_init();
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91_serial_hw_init();
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sbc35_a9g20_nand_hw_init();
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 4 | 1 << 5);
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#endif
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#ifdef CONFIG_MACB
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sbc35_a9g20_macb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
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return -1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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@ -0,0 +1,57 @@
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/*
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* Copyright (C) 2009
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* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
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* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_spi.h>
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#include <asm/arch/gpio.h>
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#include <spi.h>
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#define SBC_A9260_CS0_PIN AT91_PIN_PA3
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#define SBC_A9260_CS1_PIN AT91_PIN_PC11
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && (cs == 1 || cs == 0);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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if(slave->cs == 0)
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at91_set_gpio_value(SBC_A9260_CS0_PIN, 0);
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else if(slave->cs == 1)
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at91_set_gpio_value(SBC_A9260_CS1_PIN, 0);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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if(slave->cs == 0)
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at91_set_gpio_value(SBC_A9260_CS0_PIN, 1);
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else if(slave->cs == 1)
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at91_set_gpio_value(SBC_A9260_CS1_PIN, 1);
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}
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void spi_init_f(void)
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{
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/* everything done in board_init */
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}
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|
|
@ -75,7 +75,7 @@ void at91_serial_hw_init(void)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_HAS_DATAFLASH
|
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
|
||||||
void at91_spi0_hw_init(unsigned long cs_mask)
|
void at91_spi0_hw_init(unsigned long cs_mask)
|
||||||
{
|
{
|
||||||
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
|
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,194 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2009
|
||||||
|
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
|
||||||
|
*
|
||||||
|
* Configuation settings for the Calao SBC35-A9G20 board
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
|
||||||
|
#define CONFIG_SBC35_A9G20
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_AT91SAM9G20
|
||||||
|
|
||||||
|
#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
|
||||||
|
#define CONFIG_ENV_IS_IN_NAND
|
||||||
|
#else
|
||||||
|
#define CONFIG_ENV_IS_IN_EEPROM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ARM asynchronous clock */
|
||||||
|
#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
|
||||||
|
#define CONFIG_SYS_HZ 1000
|
||||||
|
|
||||||
|
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||||
|
|
||||||
|
#define CONFIG_ARCH_CPU_INIT
|
||||||
|
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||||
|
|
||||||
|
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||||
|
#define CONFIG_INITRD_TAG 1
|
||||||
|
|
||||||
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware drivers
|
||||||
|
*/
|
||||||
|
#define CONFIG_ATMEL_USART
|
||||||
|
#define CONFIG_USART0
|
||||||
|
#undef CONFIG_USART1
|
||||||
|
#undef CONFIG_USART2
|
||||||
|
#undef CONFIG_USART3
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options
|
||||||
|
*/
|
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||||
|
#define CONFIG_BOOTP_BOOTPATH 1
|
||||||
|
#define CONFIG_BOOTP_GATEWAY 1
|
||||||
|
#define CONFIG_BOOTP_HOSTNAME 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration.
|
||||||
|
*/
|
||||||
|
#include <config_cmd_default.h>
|
||||||
|
#undef CONFIG_CMD_BDI
|
||||||
|
#undef CONFIG_CMD_FPGA
|
||||||
|
#undef CONFIG_CMD_IMI
|
||||||
|
#undef CONFIG_CMD_IMLS
|
||||||
|
#undef CONFIG_CMD_LOADS
|
||||||
|
#undef CONFIG_CMD_SOURCE
|
||||||
|
|
||||||
|
#define CONFIG_CMD_PING 1
|
||||||
|
#define CONFIG_CMD_DHCP 1
|
||||||
|
#define CONFIG_CMD_USB 1
|
||||||
|
|
||||||
|
/* SDRAM */
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1
|
||||||
|
#define PHYS_SDRAM 0x20000000
|
||||||
|
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||||
|
|
||||||
|
/* SPI EEPROM */
|
||||||
|
#define CONFIG_SPI
|
||||||
|
#define CONFIG_CMD_SPI
|
||||||
|
#define CONFIG_ATMEL_SPI
|
||||||
|
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
|
||||||
|
|
||||||
|
#define CONFIG_CMD_EEPROM
|
||||||
|
#define CONFIG_SPI_M95XXX
|
||||||
|
#define CONFIG_SYS_EEPROM_SIZE 0x10000
|
||||||
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||||
|
|
||||||
|
/* SPI RTC */
|
||||||
|
#define CONFIG_CMD_DATE
|
||||||
|
#define CONFIG_RTC_M41T94
|
||||||
|
#define CONFIG_M41T94_SPI_BUS 0
|
||||||
|
#define CONFIG_M41T94_SPI_CS 0
|
||||||
|
|
||||||
|
/* NAND flash */
|
||||||
|
#define CONFIG_CMD_NAND
|
||||||
|
#define CONFIG_NAND_ATMEL
|
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||||
|
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||||
|
#define CONFIG_SYS_NAND_DBW_8 1
|
||||||
|
/* our ALE is AD21 */
|
||||||
|
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||||
|
/* our CLE is AD22 */
|
||||||
|
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||||
|
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||||
|
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
|
||||||
|
|
||||||
|
/* NOR flash - no real flash on this board */
|
||||||
|
#define CONFIG_SYS_NO_FLASH 1
|
||||||
|
|
||||||
|
/* Ethernet */
|
||||||
|
#define CONFIG_MACB 1
|
||||||
|
#define CONFIG_RMII 1
|
||||||
|
#define CONFIG_NET_MULTI 1
|
||||||
|
#define CONFIG_NET_RETRY_COUNT 20
|
||||||
|
#define CONFIG_RESET_PHY_R 1
|
||||||
|
#define CONFIG_MACB_SEARCH_PHY 1
|
||||||
|
|
||||||
|
/* USB */
|
||||||
|
#define CONFIG_USB_ATMEL
|
||||||
|
#define CONFIG_USB_OHCI_NEW 1
|
||||||
|
#define CONFIG_DOS_PARTITION 1
|
||||||
|
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||||
|
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
|
||||||
|
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
|
||||||
|
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||||
|
#define CONFIG_USB_STORAGE 1
|
||||||
|
#define CONFIG_CMD_FAT 1
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||||
|
|
||||||
|
/* Env in EEPROM, bootstrap + u-boot in NAND*/
|
||||||
|
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||||
|
#define CONFIG_ENV_OFFSET 0x20
|
||||||
|
#define CONFIG_ENV_SIZE 0x1000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Env, bootstrap and u-boot in NAND */
|
||||||
|
#ifdef CONFIG_ENV_IS_IN_NAND
|
||||||
|
#define CONFIG_ENV_OFFSET 0x60000
|
||||||
|
#define CONFIG_ENV_OFFSET_REDUND 0x80000
|
||||||
|
#define CONFIG_ENV_SIZE 0x20000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
|
||||||
|
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||||
|
"root=/dev/mtdblock1 " \
|
||||||
|
"mtdparts=atmel_nand:16M(kernel)ro," \
|
||||||
|
"120M(rootfs),-(other) " \
|
||||||
|
"rw rootfstype=jffs2"
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||||
|
|
||||||
|
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||||
|
#define CONFIG_SYS_CBSIZE 256
|
||||||
|
#define CONFIG_SYS_MAXARGS 16
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||||
|
#define CONFIG_SYS_LONGHELP 1
|
||||||
|
#define CONFIG_CMDLINE_EDITING 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Size of malloc() pool
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||||
|
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
|
#error CONFIG_USE_IRQ not supported
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue