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Merge with git+ssh://fifi/home/wd/git/u-boot/master

This commit is contained in:
Wolfgang Denk 2006-10-08 22:19:41 +02:00
parent eac5ba3e59 ac611700e5
commit 9444b8818f
2 changed files with 5 additions and 2 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Fix comments in include/ppc440.h
Patch by Martin Hicks, 16 Jun 2006
* Update for CAM5200 board: * Update for CAM5200 board:
- Map in a additional chip selects CS4 and CS5. - Map in a additional chip selects CS4 and CS5.
- Modify the port configration, configure six UARTs and no PCI, - Modify the port configration, configure six UARTs and no PCI,

4
include/ppc440.h
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@ -1570,8 +1570,8 @@
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440GX) #if defined(CONFIG_440GX)
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#endif /* CONFIG_440GX */ #endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */