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at91: Add support for the AT91 slow clock controller 

This is available on AT91SAM9G45. Add the peripheral address and flag
definitions.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
This commit is contained in:
Andre Renaud 2016-05-05 07:28:05 -06:00 committed by Andreas Bießmann
parent 152ac5fabf
commit 9095846655
2 changed files with 22 additions and 0 deletions
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21
arch/arm/mach-at91/include/mach/at91_sck.h Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (C) 2016 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91_SCK_H
#define AT91_SCK_H
/*
* SCKCR flags
*/
#define AT91SAM9G45_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
#define AT91SAM9G45_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
#define AT91SAM9G45_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
#define AT91SAM9G45_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
#define AT91SAM9G45_SCKCR_OSCSEL_RC (0 << 3)
#define AT91SAM9G45_SCKCR_OSCSEL_32 (1 << 3)
#endif

1
arch/arm/mach-at91/include/mach/at91sam9g45.h
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@ -109,6 +109,7 @@
#define ATMEL_BASE_RTT 0xfffffd20
#define ATMEL_BASE_PIT 0xfffffd30
#define ATMEL_BASE_WDT 0xfffffd40
#define ATMEL_BASE_SCKCR 0xfffffd50
#define ATMEL_BASE_GPBR 0xfffffd60
#define ATMEL_BASE_RTC 0xfffffdb0
/* Reserved: 0xfffffdc0 - 0xffffffff */