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mx6: clock: Fix the logic for reading axi_alt_sel 

According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:

"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "

The current logic is inverted, so fix it to match the reference manual.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Fabio Estevam 2016-07-18 10:19:28 -03:00 committed by Stefano Babic
parent 95cee94bd8
commit 8f2e2f15ff
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv7/mx6/clock.c
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@ -433,9 +433,9 @@ static u32 get_axi_clk(void)
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
else
root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
else
root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
} else } else
root_freq = get_periph_clk(); root_freq = get_periph_clk();