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ddr: altera: Fix scc_mgr_set() argument order 

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
This commit is contained in:
Marek Vasut 2016-04-04 17:28:16 +02:00
parent bba7711092
commit 8e9e62c946
1 changed files with 1 additions and 1 deletions
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2
drivers/ddr/altera/sequencer.c
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@ -279,7 +279,7 @@ static void scc_mgr_initialize(void)
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
}
}