arm: rmobile: Add supoprt for KMC KZM-A9-GT board
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 512MB DDR2-SDRAM - 16MB NOR Flash memory - Serial console (SCIF) - Ethernet (SMSC) - I2C Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Albert ARIBAUD
parent
b045a23773
commit
8d811ca36a
|
|
@ -990,6 +990,10 @@ Zhong Hongbo <bocui107@gmail.com>
|
|||
|
||||
SMDK6400 ARM1176 (S3C6400 SoC)
|
||||
|
||||
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
|
||||
kzm9g SH73A0 (RMOBILE SoC)
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Unknown / orphaned boards:
|
||||
|
|
|
|||
|
|
@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type;
|
|||
#define MACH_TYPE_UBISYS_P9D_EVP 3493
|
||||
#define MACH_TYPE_ATDGP318 3494
|
||||
#define MACH_TYPE_OMAP5_SEVM 3777
|
||||
#define MACH_TYPE_KZM9G 4140
|
||||
|
||||
#ifdef CONFIG_ARCH_EBSA110
|
||||
# ifdef machine_arch_type
|
||||
|
|
@ -14222,6 +14223,18 @@ extern unsigned int __machine_arch_type;
|
|||
# define machine_is_omap5_sevm() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_KZM9G
|
||||
# ifdef machine_arch_type
|
||||
# undef machine_arch_type
|
||||
# define machine_arch_type __machine_arch_type
|
||||
# else
|
||||
# define machine_arch_type MACH_TYPE_KZM9G
|
||||
# endif
|
||||
# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G)
|
||||
#else
|
||||
# define machine_is_kzm9g() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These have not yet been registered
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
# (C) Copyright 2012 Renesas Solutions Corp.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := kzm9g.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj) .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,372 @@
|
|||
/*
|
||||
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
* (C) Copyright 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define CS0BCR_D (0x06C00400)
|
||||
#define CS4BCR_D (0x06C00400)
|
||||
#define CS0WCR_D (0x55062C42)
|
||||
#define CS4WCR_D (0x19051443)
|
||||
#define CMNCR_BROMMD0 (1 << 21)
|
||||
#define CMNCR_BROMMD1 (1 << 22)
|
||||
#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
|
||||
#define VCLKCR1_D (0x27)
|
||||
|
||||
#define SMSTPCR1_CMT0 (1 << 24)
|
||||
#define SMSTPCR1_I2C0 (1 << 16)
|
||||
#define SMSTPCR3_USB (1 << 22)
|
||||
|
||||
#define PORT32CR (0xE6051020)
|
||||
#define PORT33CR (0xE6051021)
|
||||
#define PORT34CR (0xE6051022)
|
||||
#define PORT35CR (0xE6051023)
|
||||
|
||||
static int cmp_loop(u32 *addr, u32 data, u32 cmp)
|
||||
{
|
||||
int err = -1;
|
||||
int timeout = 100;
|
||||
u32 value;
|
||||
|
||||
while (timeout > 0) {
|
||||
value = readl(addr);
|
||||
if ((value & data) == cmp) {
|
||||
err = 0;
|
||||
break;
|
||||
}
|
||||
timeout--;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/* SBSC Init function */
|
||||
static void sbsc_init(struct sh73a0_sbsc *sbsc)
|
||||
{
|
||||
writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
|
||||
writel(0x5, &sbsc->sdgencnt);
|
||||
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
|
||||
|
||||
writel(0xacc90159, &sbsc->sdcr0);
|
||||
writel(0x00010059, &sbsc->sdcr1);
|
||||
writel(0x50874114, &sbsc->sdwcrc0);
|
||||
writel(0x33199b37, &sbsc->sdwcrc1);
|
||||
writel(0x008f2313, &sbsc->sdwcrc2);
|
||||
writel(0x31020707, &sbsc->sdwcr00);
|
||||
writel(0x0017040a, &sbsc->sdwcr01);
|
||||
writel(0x31020707, &sbsc->sdwcr10);
|
||||
writel(0x0017040a, &sbsc->sdwcr11);
|
||||
writel(0x05555555, &sbsc->sddrvcr0);
|
||||
writel(0x30000000, &sbsc->sdwcr2);
|
||||
|
||||
writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
|
||||
cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
|
||||
|
||||
writel(0x00002710, &sbsc->sdgencnt);
|
||||
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
|
||||
|
||||
writel(0x0000003f, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1A);
|
||||
writel(0x000001f4, &sbsc->sdgencnt);
|
||||
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
|
||||
|
||||
writel(0x0000ff0a, &sbsc->sdmracr0);
|
||||
if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
|
||||
writel(0x0, SDMRA3A);
|
||||
else
|
||||
writel(0x0, SDMRA3B);
|
||||
|
||||
writel(0x00000032, &sbsc->sdgencnt);
|
||||
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
|
||||
|
||||
if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
|
||||
writel(0x00002201, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1A);
|
||||
writel(0x00000402, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1A);
|
||||
writel(0x00000403, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1A);
|
||||
writel(0x0, SDMRA2A);
|
||||
} else {
|
||||
writel(0x00002201, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1B);
|
||||
writel(0x00000402, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1B);
|
||||
writel(0x00000403, &sbsc->sdmracr0);
|
||||
writel(0x0, SDMRA1B);
|
||||
writel(0x0, SDMRA2B);
|
||||
}
|
||||
|
||||
writel(0x88800004, &sbsc->sdmrtmpcr);
|
||||
writel(0x00000004, &sbsc->sdmrtmpmsk);
|
||||
writel(0xa55a0032, &sbsc->rtcor);
|
||||
writel(0xa55a000c, &sbsc->rtcorh);
|
||||
writel(0xa55a2048, &sbsc->rtcsr);
|
||||
writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
|
||||
writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
|
||||
writel(0xfff20000, &sbsc->zqccr);
|
||||
|
||||
/* SCBS2 only */
|
||||
if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
|
||||
writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
|
||||
writel(0xa5390000, &sbsc->dphycnt1);
|
||||
writel(0x00001200, &sbsc->dphycnt0);
|
||||
writel(0x07ce0000, &sbsc->dphycnt1);
|
||||
writel(0x00001247, &sbsc->dphycnt0);
|
||||
cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
|
||||
writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
|
||||
}
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
|
||||
struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
|
||||
struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
|
||||
(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
|
||||
struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
|
||||
struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
|
||||
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
|
||||
struct sh73a0_hpb_bscr *hpb_bscr =
|
||||
(struct sh73a0_hpb_bscr *)HPBSCR_BASE;
|
||||
|
||||
/* Watchdog init */
|
||||
writew(0xA507, &rwdt->rwtcsra0);
|
||||
|
||||
/* Secure control register Init */
|
||||
#define LIFEC_SEC_SRC_BIT (1 << 15)
|
||||
writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
|
||||
|
||||
clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
|
||||
clrbits_le32(&cpg->smstpcr2, (1 << 18));
|
||||
clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
|
||||
writel(0x0, &cpg->pllecr);
|
||||
|
||||
cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
|
||||
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
|
||||
|
||||
writel(0x2D000000, &cpg->pll0cr);
|
||||
writel(0x17100000, &cpg->pll1cr);
|
||||
writel(0x96235880, &cpg->frqcrb);
|
||||
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
|
||||
|
||||
writel(0xB, &cpg->flckcr);
|
||||
clrbits_le32(&cpg->smstpcr0, (1 << 1));
|
||||
|
||||
clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
|
||||
writel(0x0514, &hpb_bscr->smgpiotime);
|
||||
writel(0x0514, &hpb_bscr->smcmt2time);
|
||||
writel(0x0514, &hpb_bscr->smcpgtime);
|
||||
writel(0x0514, &hpb_bscr->smsysctime);
|
||||
|
||||
writel(0x00092000, &cpg->dvfscr4);
|
||||
writel(0x000000DC, &cpg->dvfscr5);
|
||||
writel(0x0, &cpg->pllecr);
|
||||
cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
|
||||
|
||||
/* FRQCR Init */
|
||||
writel(0x0012453C, &cpg->frqcra);
|
||||
writel(0x80331350, &cpg->frqcrb);
|
||||
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
|
||||
writel(0x00000B0B, &cpg->frqcrd);
|
||||
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
|
||||
|
||||
/* Clock Init */
|
||||
writel(0x00000003, PCLKCR);
|
||||
writel(0x0000012F, &cpg->vclkcr1);
|
||||
writel(0x00000119, &cpg->vclkcr2);
|
||||
writel(0x00000119, &cpg->vclkcr3);
|
||||
writel(0x00000002, &cpg->zbckcr);
|
||||
writel(0x00000005, &cpg->flckcr);
|
||||
writel(0x00000080, &cpg->sd0ckcr);
|
||||
writel(0x00000080, &cpg->sd1ckcr);
|
||||
writel(0x00000080, &cpg->sd2ckcr);
|
||||
writel(0x0000003F, &cpg->fsiackcr);
|
||||
writel(0x0000003F, &cpg->fsibckcr);
|
||||
writel(0x00000080, &cpg->subckcr);
|
||||
writel(0x0000000B, &cpg->spuackcr);
|
||||
writel(0x0000000B, &cpg->spuvckcr);
|
||||
writel(0x0000013F, &cpg->msuckcr);
|
||||
writel(0x00000080, &cpg->hsickcr);
|
||||
writel(0x0000003F, &cpg->mfck1cr);
|
||||
writel(0x0000003F, &cpg->mfck2cr);
|
||||
writel(0x00000107, &cpg->dsitckcr);
|
||||
writel(0x00000313, &cpg->dsi0pckcr);
|
||||
writel(0x0000130D, &cpg->dsi1pckcr);
|
||||
writel(0x2A800E0E, &cpg->dsi0phycr);
|
||||
writel(0x1E000000, &cpg->pll0cr);
|
||||
writel(0x2D000000, &cpg->pll0cr);
|
||||
writel(0x17100000, &cpg->pll1cr);
|
||||
writel(0x27000080, &cpg->pll2cr);
|
||||
writel(0x1D000000, &cpg->pll3cr);
|
||||
writel(0x00080000, &cpg->pll0stpcr);
|
||||
writel(0x000120C0, &cpg->pll1stpcr);
|
||||
writel(0x00012000, &cpg->pll2stpcr);
|
||||
writel(0x00000030, &cpg->pll3stpcr);
|
||||
|
||||
writel(0x0000000B, &cpg->pllecr);
|
||||
cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
|
||||
|
||||
writel(0x000120F0, &cpg->dvfscr3);
|
||||
writel(0x00000020, &cpg->mpmode);
|
||||
writel(0x0000028A, &cpg->vrefcr);
|
||||
writel(0xE4628087, &cpg->rmstpcr0);
|
||||
writel(0xFFFFFFFF, &cpg->rmstpcr1);
|
||||
writel(0x53FFFFFF, &cpg->rmstpcr2);
|
||||
writel(0xFFFFFFFF, &cpg->rmstpcr3);
|
||||
writel(0x00800D3D, &cpg->rmstpcr4);
|
||||
writel(0xFFFFF3FF, &cpg->rmstpcr5);
|
||||
writel(0x00000000, &cpg->smstpcr2);
|
||||
writel(0x00040000, &cpg_srcr->srcr2);
|
||||
|
||||
clrbits_le32(&cpg->pllecr, (1 << 3));
|
||||
cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
|
||||
|
||||
writel(0x00000001, &hpb->hpbctrl6);
|
||||
cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
|
||||
|
||||
writel(0x00001414, &cpg->frqcrd);
|
||||
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
|
||||
|
||||
writel(0x1d000000, &cpg->pll3cr);
|
||||
setbits_le32(&cpg->pllecr, (1 << 3));
|
||||
cmp_loop(&cpg->pllecr, 0x800, 0x800);
|
||||
|
||||
/* SBSC1 Init*/
|
||||
sbsc_init(sbsc1);
|
||||
|
||||
/* SBSC2 Init*/
|
||||
sbsc_init(sbsc2);
|
||||
|
||||
writel(0x00000b0b, &cpg->frqcrd);
|
||||
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
|
||||
struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
|
||||
struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
|
||||
(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
|
||||
|
||||
writel(CS0BCR_D, &bsc->cs0bcr);
|
||||
writel(CS4BCR_D, &bsc->cs4bcr);
|
||||
writel(CS0WCR_D, &bsc->cs0wcr);
|
||||
writel(CS4WCR_D, &bsc->cs4wcr);
|
||||
|
||||
clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
|
||||
|
||||
clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
|
||||
clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
|
||||
clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
|
||||
clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
|
||||
writel(VCLKCR1_D, &cpg->vclkcr1);
|
||||
|
||||
/* Setup SCIF4 / workaround */
|
||||
writeb(0x12, PORT32CR);
|
||||
writeb(0x22, PORT33CR);
|
||||
writeb(0x12, PORT34CR);
|
||||
writeb(0x22, PORT35CR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* SCIFA 4 */
|
||||
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
|
||||
|
||||
/* Ethernet/SMSC */
|
||||
gpio_request(GPIO_PORT224, NULL);
|
||||
gpio_direction_input(GPIO_PORT224);
|
||||
|
||||
/* SMSC/USB */
|
||||
gpio_request(GPIO_FN_CS4_, NULL);
|
||||
|
||||
/* MMCIF */
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
|
||||
|
||||
/* SDHI */
|
||||
gpio_request(GPIO_FN_SDHIWP0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
|
||||
gpio_request(GPIO_PORT15, NULL);
|
||||
gpio_direction_output(GPIO_PORT15, 1);
|
||||
|
||||
/* I2C */
|
||||
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
|
||||
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
|
||||
|
||||
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rmobile_sysinfo sysinfo = {
|
||||
CONFIG_RMOBILE_BOARD_STRING
|
||||
};
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret = 0;
|
||||
#ifdef CONFIG_SMC911X
|
||||
ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
|
|
@ -272,6 +272,7 @@ ventana arm armv7:arm720t ventana nvidia
|
|||
whistler arm armv7:arm720t whistler nvidia tegra20
|
||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||
snowball arm armv7 snowball st-ericsson u8500
|
||||
kzm9g arm armv7 kzm9g kmc rmobile
|
||||
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
|
||||
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
|
||||
actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
|
||||
|
|
|
|||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __KZM9G_H
|
||||
#define __KZM9G_H
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#define CONFIG_ARM_CORTEXA9
|
||||
#define CONFIG_RMOBILE
|
||||
#define CONFIG_SH73A0
|
||||
#define CONFIG_KZM_A9_GT
|
||||
#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_L2_OFF
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#define CONFIG_BAUDRATE (115200)
|
||||
#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
|
||||
#define CONFIG_INTEGRATOR
|
||||
#define CONFIG_ARCH_CINTEGRATOR
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#define KZM_SDRAM_BASE (0x40000000)
|
||||
#define PHYS_SDRAM KZM_SDRAM_BASE
|
||||
#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
#define CONFIG_NR_DRAM_BANKS (1)
|
||||
|
||||
/* NOR Flash */
|
||||
#define KZM_FLASH_BASE (0x00000000)
|
||||
#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (512)
|
||||
|
||||
/* prompt */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE
|
||||
#define CONFIG_CONS_SCIF4
|
||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
|
||||
#undef CONFIG_SYS_ALT_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
|
||||
#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_SDRAM_BASE KZM_SDRAM_BASE
|
||||
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE (256)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
|
||||
#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
|
||||
#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
|
||||
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
|
||||
#undef CONFIG_SYS_FLASH_PROTECTION
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
/* GPIO / PFC */
|
||||
#define CONFIG_SH_GPIO_PFC
|
||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ (48000000)
|
||||
#define CONFIG_SYS_CPU_CLK (1196000000)
|
||||
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
|
||||
#define CFG_HZ (1000)
|
||||
#define CONFIG_SYS_HZ CFG_HZ
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE (0x10000000)
|
||||
#define CONFIG_SMC911X_32_BIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SH_I2C 1
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS (2)
|
||||
#define CONFIG_SYS_I2C_MODULE
|
||||
#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE (0x7F)
|
||||
#define CONFIG_SH_I2C_DATA_HIGH (4)
|
||||
#define CONFIG_SH_I2C_DATA_LOW (5)
|
||||
#define CONFIG_SH_I2C_CLOCK (41666666)
|
||||
#define CONFIG_SH_I2C_BASE0 (0xE6820000)
|
||||
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
|
||||
|
||||
#endif /* __KZM9G_H */
|
||||
Loading…
Reference in New Issue